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| 型号： | MAX11008EVC16 |
| 厂商： | Maxim Integrated |
| 文件页数： | 56/67页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT MAX11008 |
| 标准包装： | 1 |
| 系列： | * |
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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 14. Alarm Hardware Configuration Register
DATA BITS
D[15:11]
BIT NAME
Unused
RESET STATE
XXXXX
Unused bits.
FUNCTION
ADC average monitor enable bit. Set AVGMON to 1 to average the ADC
sample. The ADC average is written to the FIFO. The tracking average has a
D10*
AVGMON
0
unique channel tag and is distinguishable from the raw sample. The average
monitoring is automatically suspended when in LUT streaming and message
modes. ADCMON and AVGMON cannot be active at the same time.
Channel 2 temperature alarm select bit. Set to 1 to configure the channel 2
temperature alarm to monitor the internal temperature sensor instead of the
D9
INTEMP2
0
external temperature sensor. The status of the alarm is indicated by the
channel 2 temperature flags in the flag register. The current-sense alarm for
channel 2 is no longer available in this mode.
ALARM comparator enable bit. Set to 1 to configure the ALARM output for
D8
ALMCOMP
0
comparator mode. Set to 0 to configure the ALARM output for interrupt
mode.
D[7:6]
D[5:4]
D[3:2]
D1
D0
ALMHYST[1:0]
ALMCLMP2[1:0
ALMCLMP1[1:0
ALMPOL
ALMOPEN
00
00
00
0
0
ALARM hysteresis select bits. See Table 14a.
Channel 2 clamp-mode select bits. See Table 14b.
Channel 1 clamp-mode select bits. See Table 14b.
ALARM polarity select bit. Set to 1 to configure the ALARM output to be
active-low. Set to 0 for active-high.
ALARM output configuration select bit. Set to 1 for open-drain ALARM
output. Set to 0 for push-pull ALARM output.
X = Don’t care.
*Write-only.
Table 14a. ALARM Hysteresis Select Bits (ALMHYST[1:0])
ALMHYST1
0
0
1
1
ALMHYST0
0
1
0
1
8 LSBs of hysteresis (+1°C)
16 LSBs of hysteresis (+2°C)
32 LSBs of hysteresis (+4°C)
64 LSBs of hysteresis (+8°C)
ALARM HYSTERESIS SELECT
Software Shutdown Register (SSHUT) (Write Only)
Write to the Software Shutdown register to power down
the MAX11008 or specific sections of the MAX11008 to
optimize power consumption (see Table 21). Bits
D[15:6] are don’t-care bits.
Set FULLPD to 1 to power down all sections of the
MAX11008 except for the serial interface. FULLPD
takes precedence over all of the other power-down
bits. Any commands (other than writing to the Software
Shutdown register) sent to the MAX11008 while in full
power-down mode are ignored. Set FULLPD to 0 to exit
full power-down mode.
Set FBGON to 1 to force the internal voltage reference
to remain powered up. This optimizes ADC conversion
times since the internal voltage reference does not
automatically power down in between conversions
(power-up time for internal reference is typically 50μs),
but it also increases the power dissipation of the
MAX11008. Set FBGON to 0 to power the internal volt-
age reference on and off as required by the ADC.
Set WDGPD to 1 to power down the internal watchdog
oscillator. The watchdog oscillator monitors the internal
circuit’s operation. It is not accessible outside of the
MAX11008. Power down the internal watchdog ocillator
when entering LUS streaming mode.
56
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