参数资料
型号: MAX14830ETM+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 微控制器/微处理器
英文描述: SERIAL COMM CONTROLLER, QCC48
封装: 7 X 7 MM, ROHS COMPLIANT, TQFN-48
文件页数: 36/68页
文件大小: 2356K
代理商: MAX14830ETM+
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
41
LCR—Line Control Register
Bit 7: RTSbit
The RTSbit provides direct control of the RTS_ output logic. If RTSbit is set to 1, then RTS_ is set to logic-high. The
RTSbit only works when CLKSource[7]: CLKtoRTS is set to 0.
Bit 6: TxBreak
Set TxBreak to 1 to generate a line break whereby the TX_ output is held low. TX_ output remains low until TxBreak is
set to 0.
Bit 5: ForceParity
The ForceParity bit enables forced parity, as used in 9-bit multidrop communication. Set both LCR[3]: ParityEn and
ForceParity to 1 to use forced parity. The parity bit is forced high by the transmitter if LCR[4]: EvenParity is low. The
parity bit is forced low if the EvenParity bit is high.
Bit 4: EvenParity
Set the EvenParity bit to 1 to generate even parity by the transmitter and parity is checked by the receiver. Odd parity
generation and checking are used if EvenParity is set low.
Bit 3: ParityEn
The ParityEn bit enables the use of a parity bit on the TX_ and RX_ interfaces. Set the ParityEn bit to 0 to disable parity
usage.
When the ParityEn bit is 1, the transmitter generates the parity bit as defined in LCR[4], and the receiver checks the
parity bit.
Bit 2: StopBits
This defines the number of STOP bits and depends on the length of the word programmed in LCR[1:0] (Table 2). When
LCR[2] is high and the word length is 5, the transmitter generates a word with a STOP bit length equal to 1.5. Under
these conditions, the receiver recognizes a STOP bit length greater than a 1-bit duration.
Bits 1, 0: Length[n]
The Length[n] bits configure the length of the words that the transmitter generates and the receiver checks for at the
asynchronous TX_ and RX_ interfaces (Table 3).
Table 2. StopBits Truth Table
Table 3. Length_ Truth Table
ADDRESS:
0x0B
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
RTSbit
TxBreak
ForceParity
EvenParity
ParityEn
StopBits
Length1
Length0
RESET
0
1
0
1
StopBits
BIT
WORD LENGTH
STOP BIT LENGTH
0
5, 6, 7, 8
1
5
1–1.5
1
6, 7, 8
2
Length1
Length0
WORD LENGTH
0
5
0
1
6
1
0
7
1
8
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