参数资料
型号: MAX14830ETM+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 微控制器/微处理器
英文描述: SERIAL COMM CONTROLLER, QCC48
封装: 7 X 7 MM, ROHS COMPLIANT, TQFN-48
文件页数: 7/68页
文件大小: 2356K
代理商: MAX14830ETM+
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
15
Pin Configuration
Pin Description
TOP VIEW
MAX14830
TQFN
(7mm
× 7mm)
13
14
15
16
17
18
19
20
21
22
23
24
GPIO2
GPIO3
RX0
TX0
GPIO4
GPIO5
GPIO6
GPIO7
48
47
*EP
*CONNECT EP TO AGND.
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10 11 12
V18
VA
AGND
XIN
XOUT
VEXT
TX3
RX3
CTS3
RTS3
GPIO15
GPIO14
GPIO1
GPIO0
DGND
V L
RST
MOSI/A1
SCLK/SCL
MISO/SDA
LDOEN
36 35 34 33 32 31 30 29 28 27 26 25
RX1
TX1
GPIO8
GPIO9
GPIO10
GPIO11
RX2
TX2
GPIO12
GPIO13
SPI/I2C
CS/A0
IRQ
RTS0
CTS0
RTS1
RTS2
CTS2
CTS1
+
PIN
NAME
FUNCTION
1
SPI/I2C
SPI or Active-Low I2C Selector Input. Drive SPI/I2C high to enable SPI. Drive SPI/I2C low to enable I2C.
2
LDOEN
LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN low to disable the
internal LDO. When LDOEN is low, V18 can be supplied by an external voltage source.
3
MISO/SDA Serial-Data Output. When SPI/I2C is high, MISO/SDA functions as the MISO, SPI serial-data output.
When SPI/I2C is low, MISO/SDA functions as the SDA, I2C serial-data input/output.
4
SCLK/SCL Serial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK, SPI serial-clock input (up
to 26MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I2C serial-clock input (up to 1MHz).
5
CS/A0
Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI
active-low chip-select input. When SPI/I2C is low, CS/A0 functions as the A0, I2C device address pro-
gramming input. Connect CS/A0 to SDA, SCL, DGND, or VL when SPI/I2C is low.
6
MOSI/A1
Serial-Data and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the MOSI, SPI serial-
data input. When SPI/I2C is low, MOSI/A1 functions as the A1, I2C device address programming input.
Connect MOSI/A1 to SDA, SCL, DGND, or VL when SPI/I2C is low.
7
IRQ
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending.
8
RST
Active-Low Reset Input. Drive RST low to force all of the UARTs into hardware reset mode. In hardware
reset mode, the oscillator and the internal PLL are shut down and there is no clock activity.
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