参数资料
型号: MAX14830ETM+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 微控制器/微处理器
英文描述: SERIAL COMM CONTROLLER, QCC48
封装: 7 X 7 MM, ROHS COMPLIANT, TQFN-48
文件页数: 44/68页
文件大小: 2356K
代理商: MAX14830ETM+
MAX14830
Quad Serial UART with 128-Word FIFOs
and Internal Oscillator
49
GPIOConfg—GPIO Configuration Register
Each UART has four GPIOs that can be configured as inputs or outputs and can be operated in push-pull or open-drain
mode. The reference clock must be active for the GPIOs to work.
Bits 7–4: GP[n]OD
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7,
UART2: GPIO8–GPIO11, UART3: GPIO12–GPIO15. For example, for UART0: Bit 4 is GP0OD, Bit 5 is GP1OD, Bit 6 is
GP2OD, and Bit 7 is GP3OD (see Table 5).
Set GP[n]OD bits to 0 to configure the GPIO_s as push-pull outputs, if configured as outputs in GPIOConfg[3:0].
Set the GP[n]OD bits to 1 to configure to open-drain output operation.
When configured as inputs in GPIOConfg[3:0], the GPIO_s are high-impedance inputs with weak pulldowns.
Bits 3–0: GP[n]Out
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7,
UART2: GPIO8–GPIO11, UART3: GPIO12–GPIO15. For example, for UART0: Bit 0 is GP0Out, Bit 1 is GP1Out, Bit 2 is
GP2Out, and Bit 3 is GP3Out (see Table 5).
The GP[n]Out bits configure the GPIO_ to be inputs or outputs. Set the GP[n]Out bits to 1 to configure the associated
GPIO_s as outputs. Set the GP[n]Out bits to 0 to configure the associated GPIOs as inputs.
Table 5. UART GPIO Assignments for GPIO Configuration
ADDRESS:
0x18
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
GP3OD
GP2OD
GP1OD
GP0OD
GP3Out
GP2Out
GP1Out
GP0Out
RESET
0
UART
GP3OD/GP3Out
GP2OD/GP2Out
GP1OD/GP1Out
GP0OD/GP0Out
UART0
GPIO3
GPIO2
GPIO1
GPIO0
UART1
GPIO7
GPIO6
GPIO5
GPIO4
UART2
GPIO11
GPIO10
GPIO9
GPIO8
UART3
GPIO15
GPIO14
GPIO13
GPIO12
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