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| 型号： | MAX1545ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/43页 |
| 文件大小： | 0K |
| 描述： | IC QUICK-PWM DUAL-PHASE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel Pentium? IV |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 1.85 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Pin Description
PIN
1
2
3
4, 5
6
7
8
9
10
11
12
NAME
TIME
TON
SUS
S0, S1
SHDN
OFS
REF
ILIM
V CC
GND
CCV
FUNCTION
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
150k Ω to 15k Ω resistor sets the clock from 100kHz to 1MHz, f SLEW = 500kHz × 30k Ω /R TIME .
On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the
DH_ on-time (see the On-Time One-Shot TON section): GND = 550kHz, REF = 300kHz, OPEN =
200kHz, V CC = 100kHz.
Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the
controller slews the output voltage to the new voltage level determined by SUS, S0–S1, and D0–D4.
The controller blanks VROK during the transition and another 24 R TIME clock cycles after the new
DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output
voltage:
3.3V or V CC (high) = suspend mode; S0–S1 low-range suspend code (Table 5),
REF = suspend mode; S0–S1 high-range suspend code (Table 5),
GND = normal operation; D0–D4 VID DAC code (Table 4).
Suspend-Mode Voltage Select Inputs. S0–S1 are four-level digital inputs that select the suspend
mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode
VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage
setting (Figure 3).
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V CC for normal
operation. Connect to ground to put the IC into its 1μA (typ) shutdown state. During the transition from
normal operation to shutdown, the output voltage ramps down at 4 times the output-voltage slew rate
programmed by the TIME pin. In shutdown mode, DLM and DLS are forced to V DD to clamp the output to
ground. Forcing SHDN to 12V ~ 15V disables both overvoltage protection and undervoltage protection
circuits, disables overlap operation, and clears the fault latch. Do not connect SHDN to >15V.
Voltage-Divider Input for Offset Control. For 0 < V OFS < 0.8V, 0.125 times the voltage at OFS is
subtracted from the output. For 1.2V < V OFS < 2V, 0.125 times the difference between REF and OFS
is added to the output. Voltages in the range of 0.8V < V OFS < 1.2V are undefined. The controller
disables the offset amplifier during suspend mode (SUS = REF or high).
2V Reference Output. Bypass to GND with a 0.22μF or greater ceramic capacitor. The reference can
source 100μA for external loads. Loading REF degrades output voltage accuracy according to the
REF load regulation error.
Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to V CC . In
adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a
0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately
V CC - 1V.
Analog Supply Voltage Input for PWM Core. Connect V CC to the system supply voltage (4.5V to 5.5V)
with a series 10 Ω resistor. Bypass to GND with a 1μF or greater ceramic capacitor, as close to the IC
as possible.
Analog Ground. Connect the MAX1519/MAX1545’s exposed pad to analog ground.
Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF, typ) capacitor from CCV
to analog ground (GND) to set the integration time constant.
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