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| 型号： | MAX1545ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 37/43页 |
| 文件大小： | 0K |
| 描述： | IC QUICK-PWM DUAL-PHASE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel Pentium? IV |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 1.85 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
V IN ( MIN ) = 2 x ?
? 1 ? 2 x ( 0 . 4 μ s x 1 . 5 / 3 . 0 μ s ?
V IN ( MIN ) = 2 x ?
? 1 ? 2 x ( 0 . 4 μ s x 1 . 0 / 3 . 0 μ s ?
If the calculated V IN(MIN) is greater than the required
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V SAG . If operation near dropout is anticipated,
calculate V SAG to be sure of adequate transient
response.
Dropout design example:
V FB = 1.4V
K MIN = 3μs for f SW = 300kHz
t OFF(MIN) = 400ns
V VPS = 3mV/A × 30A = 90mV
V DROP1 = V DROP2 = 150mV (30A load)
h = 1.5 and η OUTPH = 2
? 1 . 4 V ? 90 mV + 150 mV ?
?
+ 150 mV ? 150 mV + 90 mV = 4 . 96 V
Calculating again with h = 1 gives the absolute limit of
dropout:
? 1 . 4 V ? 90 mV + 150 mV ?
?
+ 150 mV ? 150 mV + 90 mV = 4 . 07 V
3)
4)
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Each slave controller should also have a separate
analog ground. Return the appropriate noise-sen-
sitive slave components to this plane. Since the
reference in the master is sometimes connected
to the slave, it may be necessary to couple the
analog ground in the master to the analog ground
in the slave to prevent ground offsets. A low-value
( ≤ 10 Ω ) resistor is sufficient to link the two grounds.
Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single m Ω of excess trace resistance caus-
es a measurable efficiency penalty.
Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
C_P, C_N, OAIN+, and OAIN- connections for cur-
rent limiting and voltage positioning must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy.
When trade-offs in trace lengths must be made, it
is preferable to allow the inductor-charging path to
Therefore, V IN must be greater than 4.1V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 5V.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 11). If possible, mount all of the power compo-
nents on the topside of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at
the ground terminals. This is essential for stable,
jitter-free operation.
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the V CC
bypass capacitor, REF and GNDS bypass capaci-
tors, compensation (CC_) components, and the
resistive dividers connected to ILIM and OFS.
be made longer than the discharge path. For
example, it is better to allow some extra distance
between the input capacitors and the high-side
MOSFET than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
8) Route high-speed switching nodes away from
sensitive analog areas (REF, CCV, CCI, FB, C_P,
C_N, etc). Make all pin-strap control input connec-
tions ( SHDN , ILIM, SKIP , SUS, S_, TON) to analog
ground or V CC rather than power ground or V DD .
Layout Procedure
Place the power components first, with ground termi-
nals adjacent (low-side MOSFET source, C IN , C OUT ,
and D1 anode). If possible, make all these connections
on the top layer with wide, copper-filled areas:
1) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is
1in from the controller IC).
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