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| 型号： | MAX1545ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 27/43页 |
| 文件大小： | 0K |
| 描述： | IC QUICK-PWM DUAL-PHASE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel Pentium? IV |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 1.85 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
On-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external high-
side MOSFET. Resistive losses, including the inductor,
With active current balancing, the current mismatch is
determined by the current-sense resistor values and the
offset voltage of the transconductance amplifiers:
both MOSFETs, output capacitor ESR, and PC board
copper losses in the output and ground tend to raise the
switching frequency at higher output currents. Also, the
I OS ( IBAL ) = I LM - I LS =
V OS ( IBAL )
R SENSE
( V OUT + V DROP 1 )
t ON ( V IN DROP 1 - V DROP 2 )
f SW =
I MAIN - I 2 ND MAIN ? 1 - ? MAIN ? ?
dead-time effect increases the effective on-time, reduc-
ing the switching frequency. It occurs only during forced-
PWM operation and dynamic output voltage transitions
when the inductor current reverses at light or negative
load currents. With reversed inductor current, the induc-
tor’s EMF causes LX to go high earlier than normal,
extending the on-time by a period equal to the DH-rising
dead time.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switch-
ing frequency (per phase) is:
+ V
where V DROP1 is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous recti-
fier, inductor, and PC board resistances; V DROP2 is the
sum of the parasitic voltage drops in the inductor charge
path, including high-side switch, inductor, and PC board
resistances; and t ON is the on-time as determined above.
Current Balance
Without active current-balance circuitry, the current
matching between phases depends on the MOSFET’s
on-resistance (R DS(ON) ), thermal ballasting, on-/off-time
matching, and inductance matching. For example, vari-
ation in the low-side MOSFET on-resistance (ignoring
thermal effects) results in a current mismatch that is
proportional to the on-resistance difference:
? ? R ? ?
= I
? ?
? ? R 2 ND ? ?
However, mismatches between on-times, off-times, and
inductor values increase the worst-case current imbal-
ance, making it impossible to passively guarantee
accurate current balancing.
The multiphase Quick-PWM controller integrates the
difference between the current-sense voltages and
adjusts the on-time of the secondary phase to maintain
current balance. The current balance now relies on the
accuracy of the current-sense resistors instead of the
inaccurate, thermally sensitive on-resistance of the low-
side MOSFETs.
where V OS(IBAL) is the current-balance offset specifica-
tion in the Electrical Characteristics .
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier
The multiphase Quick-PWM controllers include an inde-
pendent operational amplifier for adding gain to the volt-
age-positioning sense path. The voltage-positioning
gain allows the use of low-value current-sense resistors
in order to minimize power dissipation. This 3MHz gain-
bandwidth amplifier was designed with low offset volt-
age (70μV, typ) to meet the IMVP output accuracy
requirements.
The inverting (OAIN-) and noninverting (OAIN+) inputs
are used to differentially sense the voltage across the
voltage-positioning sense resistor. The op amp’s output is
internally connected to the regulator’s feedback input
(FB). The op amp should be configured as a noninvert-
ing, differential amplifier, as shown in Figure 10. The
voltage-positioning slope is set by properly selecting the
feedback resistor connected from FB to OAIN- (see the
Setting Voltage Positioning section). For applications
using a slave controller, additional differential input
resistors (summing configuration) can be connected to
the slave’s voltage-positioning sense resistor. Summing
together both the master and slave current-sense signals
ensures that the voltage-positioning slope remains con-
stant when the slave controller is disabled.
The controller also uses the amplifier for remote output
sensing (FBS) by summing the remote-sense voltage
into the positive terminal of the voltage-positioning
amplifier (Figure 10).
In applications that do not require voltage-positioning
gain, the amplifier can be disabled by connecting the
OAIN- pin directly to V CC . The disabled amplifier’s out-
put becomes high impedance, guaranteeing that the
unused amplifier does not corrupt the FB input signal.
The logic threshold to disable the op amp is approxi-
mately V CC - 1V.
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