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| 型号： | MAX1545ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/43页 |
| 文件大小： | 0K |
| 描述： | IC QUICK-PWM DUAL-PHASE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel Pentium? IV |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 1.85 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 3. Operating Mode Truth Table
SHDN
SUS
SKIP
OFS
OUTPUT
VOLTAGE
OPERATING MODE
Low-Power Shutdown Mode. DL_ is forced high, DH_ is
GND
x
x
x
GND
forced low, and the PWM controller is disabled. The supply
current drops to 1μA (typ).
V CC
V CC
V CC
V CC
GND
x
GND
REF
or
high
V CC
REF
or
GND
x
x
GND or REF
GND or REF
0 to 0.8V
or
1.2V to 2V
x
D0–D4
(no offset)
D0–D4
(no offset)
D0–D4
(plus offset)
SUS, S0–S1
(no offset)
Normal Operation. The no-load output voltage is determined by
the selected VID DAC code (CODE and D0–D4, Table 4).
Pulse-Skipping Operation. When SKIP is pulled low, the
MAX1519/MAX1545 immediately enter pulse-skipping
operation, allowing automatic PWM/PFM switchover under
light loads. The VROK upper threshold is blanked.
Deep-Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (CODE and D0–D4, Table 4),
plus the offset voltage set by OFS.
Suspend Mode. The no-load output voltage is determined by
the selected suspend code (SUS, S0–S1, Table 5),
overriding all other active modes of operation.
Fault Mode. The fault latch has been set by either UVP, OVP
V CC
x
x
x
GND
(MAX1545 only), or thermal shutdown. The controller
remains in FAULT mode until V CC power is cycled or SHDN
toggled.
When SHDN goes high, the reference powers up. Once
the reference voltage exceeds its UVLO threshold, the
controller evaluates the DAC target and starts switching.
The slew-rate controller ramps up from 0V in 25mV
increments to the currently selected output-voltage set-
ting (see the Power-Up Sequence section). There is no
traditional soft-start (variable current-limit) circuitry, so
full output current is available immediately.
Internal Multiplexers
The MAX1519/MAX1545 have a unique internal DAC
input multiplexer (muxes) that selects one of three differ-
ent DAC code settings for different processor states
(Figure 3). On startup, the MAX1519/MAX1545 select the
DAC code from the D0–D4 (SUS = GND) or S0–S1 (SUS
= REF or high) input decoders.
DAC Inputs (CODE, D0–D4)
During normal forced-PWM operation (SUS = GND), the
DAC programs the output voltage using code and the
D0–D4 inputs. Connect CODE to V CC or GND for the
mobile or desktop P4 setting, respectively. Do not leave
D0–D4 unconnected. D0–D4 can be changed while the
MAX1519/MAX1545 are active, initiating a transition to
a new output voltage level. Change D0–D4 together,
avoiding greater than 1μs skew between bits.
Otherwise, incorrect DAC readings can cause a partial
transition to the wrong voltage level followed by the
intended transition to the correct voltage level, length-
ening the overall transition time. The available DAC
codes and resulting output voltages are compatible
with desktop and mobile P4 (Table 4) specifications.
Four-Level Logic Inputs
TON and S0 –S1 are four-level logic inputs. These
inputs help expand the functionality of the controller
without adding an excessive number of pins. The four-
level inputs are intended to be static inputs. When left
open, an internal resistive voltage-divider sets the input
voltage to approximately 3.5V. Therefore, connect the
four-level logic inputs directly to V CC , REF, or GND
when selecting one of the other logic levels. See
Electrical Characteristics for exact logic level voltages.
Suspend Mode
When the processor enters low-power suspend mode, it
sets the regulator to a lower output voltage to reduce
power consumption. The MAX1519/MAX1545 include
20
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