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| 型号： | MAX1545ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 31/43页 |
| 文件大小： | 0K |
| 描述： | IC QUICK-PWM DUAL-PHASE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel Pentium? IV |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 1.85 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
V GS ( TH ) < V IN ? RSS ?
pling from the drain to the gate of the low-side
MOSFETs when LX switches from ground to V IN .
Applications with high input voltages and long, induc-
tive DL traces may require additional gate-to-source
capacitance to ensure fast-rising LX edges do not pull
up the low-side MOSFET’s gate voltage, causing shoot-
through currents. The capacitive coupling between LX
and DL created by the MOSFET’s gate-to-drain capaci-
tance (C RSS ), gate-to-source capacitance (C ISS -
C RSS ), and additional board parasitics should not
exceed the minimum threshold voltage:
? C ?
? C ISS ?
Lot-to-lot variation of the threshold voltage can cause
problems in marginal designs. Typically, adding a
4700pF between DL and power ground (C NL in Figure
9), close to the low-side MOSFETs, greatly reduces
coupling. Do not exceed 22nF of total gate capacitance
to prevent excessive turn-off delays.
Alternatively, shoot-through currents may be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5 Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
the turn-off time (R BST in Figure 9). Slowing down the
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Power-On Reset
Power-on reset (POR) occurs when V CC rises above
approximately 2V, resetting the fault latch, activating
boot mode, and preparing the PWM for operation. V CC
undervoltage lockout (UVLO) circuitry inhibits switch-
at the trigger input initiate a corresponding on-time
pulse (see the On-Time One-Shot section). If the V CC
voltage drops below 4.25V, it is assumed that there is
not enough supply voltage to make valid decisions. To
protect the output from overvoltage faults, the controller
activates the shutdown sequence.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
? Input voltage range: The maximum value
(V IN(MAX) ) must accommodate the worst-case high
AC adapter voltage. The minimum value (V IN(MIN) )
must account for the lowest input voltage after drops
due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
? Maximum load current: There are two values to
consider. The peak load current (I LOAD(MAX) ) deter-
mines the instantaneous component stresses and fil-
tering requirements, and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I LOAD ) determines the thermal stresses and
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents. Modern notebook CPUs generally exhibit
I LOAD = I LOAD(MAX) × 80%.
For multiphase systems, each phase supports a
fraction of the load, depending on the current bal-
ancing. When properly balanced, the load current is
evenly distributed among each phase:
ing, and forces the DL gate driver high (to enforce out-
put overvoltage protection). When V CC rises above
4.25V, the DAC inputs are sampled and the output volt-
I LOAD ( PHASE ) =
I LOAD
η TOTAL
age begins to slew to the target voltage.
For automatic startup, the battery voltage should be
present before V CC . If the Quick-PWM controller
attempts to bring the output into regulation without the
battery voltage present, the fault latch trips. Toggle the
SHDN pin to reset the fault latch.
Input Undervoltage Lockout
During startup, the V CC UVLO circuitry forces the DL
gate driver high and the DH gate driver low, inhibiting
switching until an adequate supply voltage is reached.
Once V CC rises above 4.25V, valid transitions detected
?
?
where η TOTAL is the total number of active phases.
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and V IN 2 . The opti-
mum frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
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