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| 型号： | MAX1545ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 24/43页 |
| 文件大小： | 0K |
| 描述： | IC QUICK-PWM DUAL-PHASE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器，Intel Pentium? IV |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 1.85 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 5. Suspend Mode DAC Codes
LOWER SUSPEND CODES
OUTPUT
UPPER SUSPEND CODES
OUTPUT
SUS*
S1
S0
VOLTAGE
SUS*
S1
S0
VOLTAGE
(V)
(V)
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
GND
GND
GND
GND
REF
REF
REF
REF
OPEN
OPEN
OPEN
OPEN
V CC
V CC
V CC
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
GND
GND
GND
GND
REF
REF
REF
REF
OPEN
OPEN
OPEN
OPEN
V CC
V CC
V CC
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
GND
REF
OPEN
V CC
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
* Connect the three-level SUS input to a 2.7V or greater supply (3.3V or V CC ) for an input logic level high.
troller ramps down to the 0V DAC code setting, it forces
the DL_ low-side gate-driver high, and pulls the DH_
high-side gate-driver low. Toggle SHDN or cycle the
V CC power supply below 1V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15°C.
Thermal shutdown can be disabled through the “no-fault”
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched-fault protection features and overlap mode
can complicate the process of debugging prototype
breadboards since there are (at most) a few milliseconds
in which to determine what went wrong. Therefore, a “no-
fault” test mode is provided to disable the fault protection
(overvoltage protection, undervoltage protection, and
thermal shutdown) and overlap mode. Additionally, the
test mode clears the fault latch if it has been set. The no-
fault test mode is entered by forcing 12V to 15V
on SHDN .
Multiphase Quick-PWM
5V Bias Supply (V CC and V DD )
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook’s 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
The 5V bias supply must provide V CC (PWM controller)
and V DD (gate-drive power), so the maximum current
drawn is:
I BIAS = I CC + f SW (Q G(LOW) + Q G(HIGH) )
where I CC is provided in the Electrical Characteristics ,
f SW is the switching frequency, and Q G(LOW) and Q G(HIGH)
are the MOSFET data sheet’s total gate-charge specifi-
cation limits at V GS = 5V. V+ and V DD can be tied
together if the input power source is a fixed 4.5V to 5.5V
supply. If the 5V bias supply is powered up prior to the
battery supply, the enable signal ( SHDN going from low
to high) must be delayed until the battery voltage is pre-
sent to ensure startup.
Free-Running, Constant On-Time PWM
Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator
24
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