参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 23/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 9.75V, V EE = -4.75V, V DD = 3.3V, V HHP = 17.5V, V DHV_ = 3V, V DLV_ = 0V, V DTV_ = 1.5V, SC1 = SC0 = 0V, V CPHV_ = 7.2V,
V CPLV_ = -2.2V, V CTV_ = 1.4V, V BV_ = 4V, V DGS = V GND = 0V, V CHV_ = V IVMAX_ = 2V, V CLV_ = V IVMIN_ = 1V, V COM_ = 2.5V,
V LDHV_ = 0V, V LDLV_ = 0V, V IN_ = 2.5V, V VIOS = 0V, V IIOS = 2.5V, V CLAMPHI_ = 5V, V CLAMPLO_ = 0V, V HH_ = 10V, CDRP = 0b001, RO
= 0b1000, HYST = 0b000, Z LOAD = 50 Ω , T J = +70°C to an accuracy of ±15°C, unless otherwise noted. All temperature coefficients are
measured at T J = +40°C to +100°C, unless otherwise noted.) (Note 1)
Note 29: All delay specifications are measured with DUT_ (comparator input) as the reference.
Note 30: 40MHz, 0 to 1V input to comparator, reference = 0.5V, 50% duty cycle, 250ps rise/fall time, Z S = 50 Ω , driver in term mode
with V DTV_ = 0V, and hysteresis disabled, unless otherwise specified.
Note 31: At this pulse width, the output reaches at least 90% of its nominal peak-to-peak swing. The pulse width is measured at the
crossing points of the differential outputs. 250ps rise/fall time at DUT_. Timing dispersion specifications are not guaran-
teed.
Note 32: V DUT_ = 200mVP-P, rise/fall time = 150ps, overdrive = 100mV, V DTV_ = V CM . Valid for common-mode ranges where the
signal does not exceed the operating range. Specification is worst case (slowest–fastest) over the specified range.
Note 33: For any input slew rate up to 6V/ns, no unusual behavior should be exhibited (i.e., glitching, changing polarity, etc.).
Note 34: Input to comparator is 40MHz at 0 to 1V, 50% duty cycle, 250ps 10% to 90% rise time. EQ bandwidth = 0.22/(t TCMP ^ 2 +
t TINPUT ^ 2 )^(1/2) where t TINPUT and t TCMP are the 20% to 80% transition time of the comparator input and reconstructed
output.
Note 35: Resistance measurements are made using ±2.5mA current changes in the loading instrument. Value reported is the absolute
value of the difference in measured resistance over the specified range, tested separately for each current polarity.
Note 36: Stimulus is 0 to 3V, 2.5V/ns square wave from far end of 3ns transmission line with R S = 25 Ω , clamps set to 0 and 3V.
Note 37: Change in offset over the entire operating range. Includes both gain and offset temperature effects.
Note 38: Interpretation of errors are expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point-to-
end-point range (i.e., for the ±2mA range, the full-scale range = 4mA and a 1% error = 40μA).
Note 39: With clamps enabled, the linear DUT_ current range for force voltage is defined by the clamp-current-range specification,
and the linear DUT_ voltage range for force current is defined by the linear FI V DUT_ range specification.
Note 40: For currents greater than +FSR/2, V MEAS is greater than V IIOS + 4V and for currents less than -FSR/2, V MEAS is less than
V IIOS - 4V.
Note 41: This current is supplied by the driver.
Note 42: V VIOS may be programmed to greater than 1.5V to a maximum value of 2.5V; however, the maximum valid V DUT_ value
must be reduced below 6.5V, as the maximum MEAS output is limited to 8V. Because V MEAS_ = V DUT_ + V VIOS , then
V DUT_MAX = 8V - V VIOS when V VIOS > 1.5V.
Note 43: Guaranteed by driver VHH_ and DLV_ linearity tests.
Note 44: IVMAX and IVMIN do not have separate calibration registers for MI and MV modes. Specifications apply with calibration
for each mode.
Note 45: Guaranteed by the associated accuracy test.
Note 46: The digital interface is compatible with 2.7V ≤ V DD ≤ 5V CMOS logic.
Note 47: See the Typical Operating Characteristics section.
Note 48: FIMV settling times are a function of C DUT_ and R RANGE . Increased DUT_ capacitance will increase settling time.
Note 49: The propagation delay time is guaranteed only over the force-voltage output range. Propagation delay is measured by
holding V SENSE_ steady and transitioning IVMAX_ or IVMIN_.
Note 50: Default configuration has internal 100 Ω resistors between DATA and NDATA, RCV and NRCV. Resistor terminations from
DATA, NDATA, RCV, and NRCV to a separate pin are available by special request.
Note 51: At nominal supply voltages. Total current for dual device. R L ≥ 10M Ω .
Note 52: Increasing DGS beyond 0V requires a proportional increase in the minimum supply levels. Specified ranges for all DAC
output levels are defined with respect to DGS.
Note 53: The error of the external 2.5V reference impacts the accuracy of the DAC levels; a 1% error in the 2.5V reference will trans-
late to a 1% error in the DAC level gain. Use a precision voltage reference, such as the MAX6225.
Note 54: Generate the 2.5V external reference with respect to DGS (DUT ground sense).
Note 55: Guaranteed by associated CMRR_ test.
Note 56: The comparator outputs are normally source side-terminated with 50 Ω on-die to CTV_ and at the receive side of the trans-
mission path. The comparator outputs are tested with the 50 Ω on-die source resistors only with limits relative to CTV_ twice
the values indicated.
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