参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 36/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Table 2. Driver Control
SERIAL-INTERFACE BITS
LLEAKS_ ENVHHS_ TMSEL_
LLEAKP_
DIGITAL INPUTS
ENVHHP_ RCV_
DATA_
DRIVER OUTPUT
0
0
0
0
0
0
X
1
X*
X*
0
0
1
0
X
X
X
X
0
1
X
X
X
X
1
1
1
1
1
1
0
X
1
1
1
1
X
0
X
X
0
0
1
1
1
X
X
X
0
1
X
X
X
X
X
X
Drive to DLV
Drive to DHV
High-impedance receive
Drive to DTV
Drive to VHH**
Drive to VHH**
Low leak
Low leak
*Specified DHV, DLV transition times are not altered by the state of ENVHHS_.
**PMU and active load must be disabled to drive to VHH_ ( HIZFORCE_ = 0, FMODE_ = 1, MMODE_ = 0, LDDIS_ = 1).
Table 3. Driver Slew Control
TRANSMISSION
SC1_
0
SC0_
0
DRIVER SLEW RATE (%)
100*
TYPICAL
DRIVER
LOSS
DUT
0
1
1
1
0
1
75
50
25
*The power-on-reset and RST default value.
Driver Slew Control
MAX9979
A slew-rate circuit controls the slew rate of the buffer
input. Select one of four possible slew rates according
to Table 3. The speed of the internal multiplexer sets
MUX
WAVEFORM
SHAPING
BUFFER
TRANSMISSION
LOSS
DUT
the 100% driver slew rate (see the Driver Large-Signal
Response graph in the Typical Operating
Characteristics section). SC1 and SC0 are set to 0 at
power-up or when RST is forced low.
VHH Function
VHH allows DUT_ to drive voltages up to 13V. The
VHH_ DAC, which doubles as the PMU’s CLAMPHI_ DAC,
adjusts from 0 to +13V. Table 2 indicates the control
settings required to set DUT_ to VHH_. Table 23 shows
the transfer function for the VHH_ DAC.
Driver Cable-Droop Compensation
The driver incorporates active cable-droop compensa-
tion. At high frequencies, transmission-line effects from
the DUT_ output, across the tester signal delivery path
to the device under test, can degrade the output wave-
form fidelity, resulting in a highly degraded or unusable
signal. The compensation circuit counters this degrada-
tion by adding a double time-constant decaying wave-
CDRP_
Figure 2. Cable-Droop Compensation
form to the nominal output waveform (pre-emphasis).
Figure 2 depicts a comparison between a typical driver
and the MAX9979, and shows how droop compensa-
tion counters signal degradation. Control bits CDRP0,
CDRP1, and CDRP2 vary the amplitude of the compen-
sation signal. Table 4 shows the percent compensation
as a function of control bit settings. The power-on-reset
and RST values for CDRP0, CDRP1, and CDRP2 are 0.
The specified default value is CDRP0 = 1 for Electrical
Characteristics table data.
36
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