参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 58/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
The V DAC voltages are then utilized for the various sig-
nal paths within the MAX9979 (i.e., driver level DHV_).
Each of these signal paths have inherent gain and offset
errors, denoted as _gain and _offset terms in the Level
Transfer Function column in Table 23. These error terms
are presented to convey the non-ideal gain and offset of
the signal paths—they do not have a specified value.
The GAIN CODE and OFFSET CODE features of each
DAC are designed to correct for these errors to make
the level transfer function expressions, and therefore,
the final signal path outputs (e.g., DHV_) more ideal.
Applications Information
Device Power-Up State
0x0004, 0x0008, and 0x0003, respectively. For initial
power-up values for the level-setting registers, see Table
20. Power supplies may be powered on in any sequence.
Power-Supply Considerations
Bypass each supply input to GND and REF to DGS with
0.1 μF capacitors (Figure 13). Additionally, use bulk
bypassing of at least 10μF where the power-supply
connections meet the circuit board.
Exposed Pad
The exposed pad is internally connected to ground.
Connect to a open copper PCB ground plane or
heatsink to maximize thermal performance. Not intend-
ed as an electrical connection point.
Upon power-up, the DCL enters low-leak mode and the
PMU enters high-impedance mode. The DCL control,
DCL calibration, and PMU control registers default to
Pin Configuration
TOP VIEW
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
MEAS0
DUTHI0
DUTLO0
REF
DGS
GND
DOUT
DGND
CS
1
2
3
4
5
6
7
8
9
+
MAX9979
51 GND
50 V EE
49 V CC
48 DUT0
47 V EE
46 V CC
45 PMU-S
44 PMU-F
43 V HHP
SCLK 10
DIN 11
V DD 12
LOAD 13
RST 14
42 N.C.
41 TEMP
40 V CC
39 V EE
38 DUT1
DUTLO1 15
DUTHI1 16
MEAS1 17
*EP
37 V CC
36 V EE
35 GND
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TQFN-EP-IDP
*EP = EXPOSED PAD.
58
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