参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 38/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Driver DATA Invert Mode
The DATA_/NDATA_ signals for a driver channel are
internally inverted when the INVERT_ bit in the DCL reg-
ister is asserted. The INVERT_ bit is set to 0 at power-
up or when RST is forced low.
Driver Differential Data Mode
The MAX9979 allows the drivers to be configured for
control of both channels from the channel 0
DATA0/NDATA0 inputs. This feature allows the two
channels to drive DUT nodes in parallel, providing a
25 Ω driver at twice the nominal drive current. Enable
this feature by setting the DIFFERENTIAL0 bit in the
DCL register. The DIFFERENTIAL0 bit is set to 0 at
power-up or when RST is forced low.
Driver Invert + Differential Data Mode
Combining the differential and the invert modes allows
the two channels to produce complementary outputs at
DUT0 and DUT1 from a single digital data stream at
DATA0/NDATA0. The driver block diagram (Figure 3)
shows the logic of the differential and inverted modes.
Bias Voltage Input (BV_)
Apply a voltage to BV_ that is ≥ the V IH voltage used for
the DATA_ and RCV_ inputs (V IH (DATA_, RCV_)) <
V BV < 3.5V, because there are ESD-protection diodes
between BV_ and the high-speed inputs. Failure to do
this turns on the protection diodes, degrading the
DATA_ and RCV_ signals. Input bias current for BV_ is
less than 1μA.
Driver Voltage Clamps
The voltage clamps (high and low) limit the voltage at
DUT_ and suppress reflections when the channel is
configured as a high-impedance receiver. The clamps
behave as diodes connected to the outputs of high-
current buffers (Figure 1). Internal circuitry compen-
voltages at least 0.7V outside the expected DUT_ volt-
age range when not using the clamps. Overvoltage
protection then remains active without loading DUT_.
Driver clamps are always and only enabled in driver
high-impedance mode.
High-Speed Comparators
The MAX9979 provides two independent high-speed
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (Figure 4).
Cable-droop compensation is present on both chan-
nels. Comparator outputs are a logical result of the
input conditions.
This configuration switches a 16mA current source
between the two outputs, and each output has an internal
termination resistor connected to CTV_. These resistors
are typically 50 Ω . Use alternate configurations to termi-
nate different path impedance provided that the absolute
maximum ratings are not exceeded. Note that the resistor
value also sets the voltage swing. The output provides a
nominal 400mV P-P swing with a 50 Ω load termination,
and a 50 Ω source termination. See the Electrical
Characteristics section titled High-Speed Comparators,
Logic Outputs for definition of the V OH voltage.
Single-Ended Window Comparator
Set the DIFFERENTIAL1 bit = 0 in the channel 1 DCL
register to enable the high-speed window comparator.
DAC voltages CHV_ and CLV_ control the comparator
thresholds. Table 6 shows the truth table for the com-
parators. Figure 4 shows the comparator block dia-
gram.
Table 6. Single-Ended Window
Comparator Truth Table
sates for the diode drop at 1mA clamp current. Set the
CONDITION
CH_
CL_
clamp voltages using the level-setting DACs (CPHV_
and CPLV_). The clamps are enabled only when the
driver is in the high-impedance mode. For transient
suppression, set the clamp voltages to approximately
the minimum and maximum expected DUT_ voltage
V DUT_ < V CHV_
V DUT_ < V CHV_
V DUT_ > V CHV_
V DUT_ > V CHV_
V DUT_ < V CLV_
V DUT_ > V CLV_
V DUT_ < V CLV_
V DUT_ > V CLV_
0
0
1
1
0
1
0
1
range. The optimal clamp voltages are application-spe-
cific and must be empirically determined. Set the clamp
38
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