参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 35/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
The integration of DCL and PMU functions in the
MAX9979 requires defined states to manage the inter-
action of these resources. The PMU controls supersede
those of the DCL, as described below and shown in
Table 1. Important details to keep in mind are:
? Normal high-speed DCL operation is intended only
when the PMU is in the FNMN state and the DCL is
available, as indicated by Note B in Table 1.
? Forcing LLEAKP_ = 0 immediately places the DCL
into low-leak mode, and the PMU into its high-
impedance state independent of any other pro-
grammed control bit or external control inputs.
Forcing LLEAKP_ = 1 is required to allow any other
mode of operation.
? Forcing HIZFORCE_ = 1 enables the PMU and
simultaneously forces the DCL into low-leak mode.
? Additional PMU settings such as the force and mea-
sure modes, current range, the measure output,
comparators, and the clamp features are controlled
as described later in this document.
? The MAX9979 provides calibration modes under
which both the DCL and the PMU are simultaneously
active. Forcing HIZFORCE_ = 0 ordinarily disables
the PMU, however, when LLEAKS_ is not asserted,
the FMODE_ and MMODE_ bits select these calibra-
Table 1. MAX9979 Mode Selection
tion modes. While in a calibration mode, the DCL
states are still selected by the controls normally
associated with those functions. When in a calibra-
tion mode, the PMU range A is not available. The
PMU range defaults to range B if the serial-interface
bit RS2_ = 1.
Driver
The driver uses a high-speed multiplexer to select one
of three DAC voltages (DHV_, DLV_, and DTV_), or to
select high-impedance mode. Multiplexer switching is
controlled by high-speed differential inputs
DATA_/NDATA_ and RCV_/NRCV_ and mode-control
bit TMSEL_ (see Table 2). The multiplexer output is
buffered to drive DUT_. A programmable slew-rate cir-
cuit controls the slew rate of the buffer input.
In high-impedance mode, the clamps and comparators
remain connected to DUT_, the DUT_ bias current is
less than ±2μA, and the node continues to track high-
speed signals. In low-leakage mode, the bias current at
DUT_ is further reduced to less than ±10nA, yet signal
tracking slows.
The nominal driver output resistance is 50 Ω and fea-
tures an adjustment range of ±2.5 Ω through the serial
interface in 360m Ω increments. Contact the factory for
different output resistance values.
MODES
PMU
DCL
FNMx
DRIVER
Low leak
Low leak
Low leak
Low leak
Low leak
Available
Available
Available
Low leak
Low leak
COMPARATOR
Low leak
Low leak
Low leak
Low leak
Available
Available
Available
Available
Low leak
Low leak
LOAD
Low leak
Low leak
Low leak
Low leak
Available
Available
Available
Available
Low leak
Low leak
PMU
FVMI
FVMV
FIMI
FIMV
FVMI
FIMV
FNMN
FNMV
FNMN
FNMV
FMODE_
0
0
1
1
0
0
1
1
X
X
MMODE_
0
1
0
1
0
1
0
1
0
1
LLEAKP_
1
1
1
1
1
1
1
1
0
0
HIZFORCE_
1
1
1
1
0
0
0
0
X
X
NOTE
A
A
B
A
A = Calibration modes.
B = Normal high-speed DCL operation mode.
______________________________________________________________________________________
35
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