参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 48/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
t CH
SCLK
t CSSO
t CSHO
t CL
t CSH1
t CSS1
CS
t CSWH
t DH
t DS
DIN
A7
A6
A5
A4
A3
A2
D1
D0
t RST
RST
LOAD
t DO
t CSHLD
t CLL
DOUT
A7 LAST
A6 LAST
A5 LAST
A4 LAST
A3 LAST
A2 LAST
D1 LAST
D0 LAST
A7
Figure 9. Serial-Interface Timing
Holding LOAD low during the rising edge of CS forces
the input and channel-select registers to become trans-
parent and all data transfers through these registers
directly to the control and level-setting registers.
Changes update on the rising edge of CS . Figures 10
and 11 show how LOAD and CS function, and also the
data configuration of SCLK, DIN, and DOUT.
The calibration registers change on the rising edge of
CS , regardless of the state of LOAD .
DOUT
DOUT is a buffered version of the last bit in the serial-
interface shift register. The complete contents of the
shift register can be read at DOUT during the next write
cycle. To shift data out without modifying any registers,
perform a write with address bits A4 and A5 set to 0.
Use DOUT to daisy chain multiple devices, and/or to
verify that data were properly shifted in during the pre-
vious communication.
Controlling the MAX9979
Control and level-setting registers are selected to
receive data based on the channel and mode-select
bits (A0–A7). Table 16 presents the control register bits
and their functions. Level-setting DAC data and control-
register data are contained in the 16 data bits D0–D16.
Tables 15, 16, and 17 detail the bit functions. Clock in
bit A7 first, and bit D0 last, as shown in Figure 8.
Bit A6 allows access to the DAC calibration registers.
Use the calibration registers to adjust the gain and off-
set of each DAC. Set bit A6 to write to the calibration
registers (Table 18). See the Level-Setting DACs sec-
tion for more information.
48
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