参数资料
型号: MAX9979EVKIT+
厂商: Maxim Integrated Products
文件页数: 52/60页
文件大小: 0K
描述: EVAL KIT MAX9979
标准包装: 1
系列: *
Dual 1.1Gbps Pin Electronics with Integrated
PMU and Level-Setting DACs
Table 19. Data Bit Assignments* (continued)
FUNCTION
BIT
DCL CONTROL
REGISTER**
DCL
CALIBRATION
REGISTER**
PMU CONTROL
REGISTER**
LEVEL-SETTER
REGISTER
DAC GAIN AND OFFSET
CALIBRATION REGISTERS
VIN ALL OTHERS
D11
D12
D13
D14
D15
TMUX2 = 0
TMUX3 = 0
PMU-F
PMU-S
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15 (MSB)
GCAL3
GCAL4
GCAL5
GCAL6
GCAL3
GCAL4
GCAL5
*The data bits enter the shift register in the order, MSB to LSB.
**The DCL control, DCL calibration, and PMU control registers default to 0x0004, 0x0008, and 0x0003 respectively at power-up.
Level-Setting DACs
The MAX9979 includes 28 level-setting DACs that pro-
vide the DC voltage levels for the various control and
MAX9979
monitor circuits of the 2-channel MAX9979. Some of the
DACs are shared between the MAX9979 channels, and
some perform dual functions within a channel (Figure
12). Important details about the operation of shared
DACs are:
? VIOS share a common DAC level for both channels.
VIOS DAC simultaneously updates the VIOS1 and
VIOS2 levels.
? IIOS share a common DAC level for both channels.
The IIOS DAC simultaneously updates the IIOS1 and
IIOS2 levels.
? CLAMPHI_ and VHH_ share a common DAC level.
CLAMPHI1
CHV1
CLV1
IIOS
VIOS
CLAMPHI1
VHH1
CHV1
IVMAX1 CHANNEL 1
CLV1
IVMIN1
IIOS
VIOS
VIOS
IIOS
IVMIN2
The CLAMPHI_/VHH_ DAC simultaneously updates
the CLAMPHI_ and VHH_ levels. Note that the VHH_
output is 0 to +13V. If CLAMPHI_ is set to a negative
value and the VHH_ mode is selected, the VHH_ out-
CLV2
CHV2
CLV2
IVMAX2
CHV2
VHH2
CHANNEL 2
put limits close to 0V.
? CHV_ and IVMAX_ share a common DAC level. The
CLAMPHI2
CLAMPHI2
CHV_/IVMAX_ DAC simultaneously updates the
CHV_ and IVMAX_ levels.
? CLV_ and IVMIN_ share a common DAC level. The
CLV_/IVMIN_ DAC simultaneously updates the CLV_
and IVMIN_ levels.
A 16-bit code that varies between 0x0000 and 0xFFFF
sets all DAC levels. Table 20 presents a list of the DACs
and their default values.
Figure 12. Arrangement of Shared DACs
Calibrating DAC Gain and Offset
DAC calibration registers adjust the gain and offset of
each DAC. Each DAC has at least one calibration regis-
ter. All DAC calibration registers are programmed with a
14-bit code, except VIN_, which uses a 15-bit code
(Table 19). The codes are divided into two fields, one field
each for gain (GCAL_) and offset (OCAL_). VIN_ has a 7-
bit field for gain and an 8-bit field for offset. All other DACs
have a 6-bit field for gain and an 8-bit field for offset.
52
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