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Decoupling Requirements
ON Semiconductor Advanced CMOS, as with other high-
performance, high-drive logic families, has special
decoupling and printed circuit board layout requirements.
Adhering to these requirements will ensure the maximum
advantages are gained with FACT products.
Local high frequency decoupling is required to supply
power to the chip when it is transitioning from a LOW to a
HIGH value. This power is necessary to charge the load
capacitance or drive a line impedance. Figure 1–45 displays
various VCC and ground layout schemes along with
associated impedances.
For most power distribution networks, the typical
impedance is between 50 and 100 ohms. This impedance
appears in series with the load impedance and will cause a
droop in the VCC at the part. This limits the available voltage
swing at the local node, unless some form of decoupling is
used. This drooping of rails will cause the rise and fall times
to become elongated. Consider the example described in
Figure 1–46 to calculate the amount of decoupling
necessary. This circuit utilizes an ‘AC240 driving a 100 ohm
bus from a point somewhere in the middle.
DATA BUS
100
BUFFER
1 OF 8
100 V
GROUND
PLANE
VOUT
0.1 V
IOH
0
4.9 V
4.0 ns
94 mA
Worst-Case Octal Drain = 8
× 94 mA = 0.75 Amp.
Figure 1–46. Octal Buffer Driving a 100 Ohm Bus
Buffer Output Sees Net 50
Load.
50
Load Line on IOH–VOH Characteristic
Shows Low-to-High Step of Approx. 4.8 V
Being in the middle of the bus, the driver will see two 100
ohm loads in parallel, or an effective impedance of 50 ohms.
To switch the line from rail to rail, a drive of 94 mA is
needed; more than 750 mA will be required if all eight lines
switch at once. This instantaneous current requirement will
generate a voltage across the impedance of the power lines,
causing the actual VCC at the chip to droop. This droop limits
the voltage swing available to the driver. The net effect of the
voltage droop will lengthen device rise and fall times and
slow system operation. A local decoupling capacitor is
required to act as a low impedance supply for the driver chip
during high current conditions. It will maintain the voltage
within acceptable limits and keep rise and fall times to a
minimum. The necessary values for decoupling capacitors
can be calculated with the formula given in Figure 1–47.
In this example, if the VCC droop is to be kept below 0.1
V and the edge rate equals 4 ns, a 0.03
F capacitor is
needed.
It is good practice to distribute decoupling capacitors
evenly through the logic, placing one capacitor for every
package.
Capacitor Types
Decoupling capacitors need to be of the high K ceramic
type with low equivalent series resistance (ESR), consisting
primarily of series inductance and series resistance.
Capacitors using 5ZU dielectric have suitable properties and
make a good choice for decoupling capacitors; they offer
minimum cost and effective performance.
Figure 1–47. Formula for Calculating Decoupling Capacitors
VCC BUS
VCC
ZCC
CB
BYPASS CAPACITORS
SPECIFY VCC DROOP = 0.1 V MAX.
I = 0.75 A
Q = CV
I = CV/t
C = It/V
t = 4 × 10 -9
C = 0.750
× 4 × 10-9
0.1
= 30 × 10-9 = 0.030 F
SELECT CB ≥ 0.047 F
Place one decoupling capacitor adjacent to each package driving any transmission line and distribute others evenly throughout the logic.