http://onsemi.com
16
The circuit shown in Figure 1–9 was used to compare the
power consumption of FACT versus ALS devices.
Two identical circuits were built on the same board and
driven from the same input. In the circuit, the input signal
was driven into four D-type flip-flops which act as
divide-by-2 frequency dividers. The outputs from the
flip-flops were connected to the inputs of a MC74AC38
Figure 1–10. FACT versus ALS Circuit Power
ALS CIRCUIT
STOPPED
FUNCTIONING
FACT
400
350
300
250
200
150
100
50
0
204060
80
100
FREQUENCY (MHz)
POWER
(mW)
ALS
decoder. This generated eight non-overlapping clock pulses
on the outputs of the MC74AC38, which were then
connected to an MC74AC04 inverter. The input frequency
was then varied and the power consumption was measured.
Figure 1–10 illustrates the results of these measurements.
Below 40 MHz, the FACT circuit dissipates much less
power than the ALS version. It is interesting to note that
when the frequency went to zero, the FACT circuit’s power
consumption also went to near zero; the ALS circuit
continued to dissipate almost 100 mW. Another advantage
of FACT is its capabilities above 40 MHz. At this frequency,
the first 74ALS74 D-type flip-flop ceased to operate. Once
this occurred, the entire circuit stopped working and the
power consumption fell to its quiescent value. The FACT
device, however, continued functioning beyond the limit of
the frequency generator, which was 100 MHz.
This graph shows two advantages of FACT circuits
(power and speed). FACT logic delivers increased
performance in addition to offering the power savings of
CMOS.
Refer to Section 3 for test philosophies regarding power
dissipation.
Specification Derivation
At first glance, the specifications for FACT logic might
appear to be widely spread, possibly indicating wide design
margins are required. However, several effects are reflected
in each specification.
Figures 1–11a through 1–11e illustrate how the data from
the characterization of actual devices is transformed into the
specifications that appear on the data sheet. This data is
taken from the ‘AC245.
Figure 1–11a shows the data taken (from one part) on a
typical, single path, tPHL from An to Bn, over temperature
at
5 V; there is negligible variation in the value of tPHL. The
next graph, Figure 1–11b, depicts data taken on the same
device; this set of curves represents the data on all paths A
to B and B to A. The data on this plot indicates only a small
variation for tPHL.
The graphs in Figures 1–11a and 1–11b include data at 5
V; Figure 1–11c shows the variation of delay times over the
standard 5
± 0.5 V voltage range. Note there is only a ± 6%
variation in delay time due to voltage effects.
Now refer to Figure 1–11d which illustrates the process
effects on delay time. This graph indicates that the process
effects contribute to the spread in specifications more than
any other factor in that the effects of the theoretical process
spread can increase or decrease specification times by 30%.
Because this 30% spread represents considerably more than
± 3 standard deviations, this guarantees an increase in the
manufacturability and the quality level of FACT product. To
further ensure parts within specification will pass on testers
at the limits of calibration, tester guardbands are
incorporated.
8
7
6
5
4
3
2
1
0
-60 -40 -20
0
20
40
60
80
100 120
VCC = 5 V
TEMPERATURE (°C)
Figure 1–11a. tPHL, An to Bn, Single Path