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参数资料
| 型号： | MCF5235CVM100 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | MAPBGA-256 |
| 文件页数： | 13/76页 |
| 文件大小： | 2665K |
| 代理商： | MCF5235CVM100 |
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20
MCF523x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Primary Functions
2.2.3
Mode Selection
Table 5 describes signals used in mode selection.
2.2.4
External Memory Interface Signals
Table 6 describes signals that are used for doing transactions on the external bus.
Table 5. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection
CLKMOD[1:0] Configure the clock mode after reset.
I
Reset Configuration
RCON
Indicates whether the external D[31:16] pin states affect chip
configuration at reset.
I
Table 6. External Memory Interface Signals
Signal Name
Abbreviation
Function
I/O
Address Bus
A[23:0]
The 24 dedicated address signals define the address of external byte,
word, and longword accesses. These three-state outputs are the 24
lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
Unused pins are can be configured as GPIO. The A[23:21] pins can
also be configured as CS[6:4].
O
Data Bus
D[31:0]
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
The D[15:0] pins can be configured as GPIO when using a 16-bit bus.
I/O
Byte Strobes
BS[3:0]
Define the flow of data on the data bus. During SRAM and peripheral
accesses, these output signals indicate that data is to be latched or
driven onto a byte of the data when driven low. The BS[3:0] signals are
asserted only to the memory bytes used during a read or write access.
BS0 controls access to the most significant byte lane of data, and BS3
controls access to the least significant byte lane of data.
The BS[3:0] signals are asserted during accesses to on-chip
peripherals but not to on-chip SRAM, or cache. During SDRAM
accesses, these signals act as the CAS[3:0] signals, which indicate a
byte transfers between SDRAM and the chip when driven high.
For SRAM or Flash devices, the BS[3:0] outputs should be connected
to individual byte strobe signals.
For SDRAM devices, the BS[3:0] should be connected to individual
SDRAM DQM signals. Note that most SDRAMs associate DQM3 with
the MSB, in which case BS0 should be connected to the SDRAM’s
DQM3 input.
These pins can also be configured as GPIO.
O
Output Enable
OE
Indicates when an external device can drive data during external read
cycles.
This pin can also be configured as GPIO.
O
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCF5235CVM100J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| MCF5235CVM150 | 功能描述:IC MPU 32BIT COLDF 256-MAPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:MCF523x 标准包装:330 系列:- 核心处理器:- 芯体尺寸:8/16-位 速度:40MHz 连通性:UART/USART 外围设备:DMA，PWM，WDT 输入/输出数:32 程序存储器容量:- 程序存储器类型:外部程序存储器 EEPROM 大小:- RAM 容量:- 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:100-BQFP 包装:管件 |
| MCF5235CVM150 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
| MCF5235CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| MCF5235CVM150J | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 150 MHz 256-BGA |
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