参数资料
型号: MCF5235CVM100
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封装: MAPBGA-256
文件页数: 14/76页
文件大小: 2665K
代理商: MCF5235CVM100
MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
21
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Primary Functions
Transfer Acknowledge
TA
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
This pin can also be configured as GPIO.
I
Transfer Error
Acknowledge
TEA
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
This pin can also be configured as GPIO or DMA transfer request
signal DREQ0.
I
Read/Write
R/W
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
This pin can also be configured as GPIO.
O
Transfer Size
TSIZ[1:0]
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
These pins can also be configured as GPIO or DMA transfer
acknowledge signals DACK1/DACK0.
O
Transfer Start
TS
Bus control output signal indicating the start of a transfer.
This pin can also be configured as GPIO or DMA transfer
acknowledge signal DACK2.
O
Transfer in Progress
TIP
Bus control output signal indicating bus transfer in progress.
This pin can also be configured as GPIO or DMA transfer request
signal DREQ0.
O
Chip Selects
CS[7:0]
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
CS[7:1] pins can also be configured as GPIO.
O
Table 6. External Memory Interface Signals (continued)
Signal Name
Abbreviation
Function
I/O
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