参数资料
型号: MCF5235CVM100
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封装: MAPBGA-256
文件页数: 76/76页
文件大小: 2665K
代理商: MCF5235CVM100
MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
9
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
1.3.2
V2 Core Overview
The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The
two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction
fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting
execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage
decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction
execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
MCF523x core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing
capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32
× 32 bit operations, with
support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned
integers as well as signed fractional operands as well as a complete set of instructions to process these data
types. The EMAC provides superb support for execution of DSP operations within the context of a single
processor at a minimal hardware cost.
1.3.3
Enhanced Time Processor Unit (eTPU)
The eTPU is an intelligent programmable I/O controller with its own core and memory system, allowing it
to perform complex timing and I/O management independently of the CPU. The eTPU is essentially a
co-processor designed for timing control, I/O handling, serial communications, motor control. and engine
control applications and accesses data without the host CPU’s intervention. Consequently, the host CPU
setup and service times for each timer event are minimized or eliminated.
The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500 products.
Enhancements of the eTPU include a more powerful processor which handles high-level C code efficiently
and allows for more functionality and increased performace. Although there is no compatibility at
microcode level, the eTPU maintains several features of older TPU versions and is conceptually almost
identical. The eTPU library is a superset of the standard TPU library functions modified to take advantage
of enhancements in the eTPU. These, along with a C compiler, make it relatively easy to port older
applications. By providing source code for the Motorola library, it is possible for the eTPU to support the
users own function development.
The eTPU has up to 32 timer channels in addition to having 6 Kbytes of code memory and 1.5 Kbytes of
data memory that stores software modules downloaded at boot time and that can be mixed and matched as
required for any specific application.
1.3.4
eTPU Functions
Any one of the following four sets of functions can be loaded into the device.
1.3.4.1
Set 1 (General)
PWM – Full featured Pulse Width modulation
ICOC – Input Capture / Output Compare
PFM – Pulse and frequency measurement
PPA – Pulse / Period Accumulate
SM – Stepper motor
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