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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 1/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
www.fairchildsemi.com
REV. 1.0.2 12/30/00
Features
Input clocks can be either TTL or PECL with low input to
output clock phase error
8 independent, automatically deskewed clock outputs
with up to 5ns of on-board deskew range (10ns round trip)
Controlled edge rate TTL-compatible CMOS clock
outputs capable of driving 40
PCB traces
10 to 80MHz (6510-80) input and output clock frequency
range
Less than 500ps skew between inputs at the device loads
Small-swing reference clock outputs for minimizing part-
to-part skew
Frequency multiplication or division is possible using the
M&N divider ratio
Lock output indicates PLL and deskew buffer lock
Test mode operation allows PLL and deskew buffer
bypass for board debug
Supports industry standard processors like Pentium,
Mips, SPARC, PowerPC, Alpha, etc.
General Description
The ML6510 (Super PACMan) is a Programmable
Adaptive Clock Manager which offers an ideal solution for
managing high speed synchronous clock distribution in next
generation, high speed personal computer and workstation
system designs. It provides eight channels of deskew buffers
that adaptively compensate for clock skew using only a
single trace. The input clock can be either TTL or PECL,
selected by a bit in the control register. Frequency multipli-
cation or division is possible using the M&N divider ratio,
within the maximum frequency limit. 0.5X, 1X, 2X and 4X
clocks can be easily realized.
The ML6510 is implemented using a low jitter PLL with
on-chip loop lter. The ML6510 deskew buffers adaptively
compensate for clock skew on PC boards. An internal skew
sense circuit is used to sense the skew caused by the PCB
trace and load delays. The sensing is done by detecting a
reection from the load and the skew is corrected adaptively
via a unique phase control delay circuit to provide low load-
to-load skew, at the end of the PCB traces. Additionally, the
ML6510 supports PECL reference clock outputs for use in
the generation of clock trees with minimal part-to-part skew.
The chip conguration can be programmed to generate the
desired output frequency using the internal ROM or an
external serial EEPROM or a standard two-wire serial
microprocessor interface.
System Block Diagram
CPU
CACHE
RAM
LOCAL BUS
MEMORY BUS
CACHE
CONTROLLER
MEMORY BUS
CONTROLLER
ML6510
CLK
CLOCK OUT TO
COMPONENTS
8
CLOCK SUBSYSTEM
CLOCK IN
ML6510
Series Programmable Adaptive Clock Manager
(PACMan)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
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