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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 2/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
10
REV. 1.0.2 12/30/00
Adaptive Deskew buffers
Each copy of the clock is driven by an adaptive deskew
buffer. The deskew buffer compensates for skew time auto-
matically in accordance to the ight time delay it senses
from the reection on the transmission line.
Figure 4 shows the simplied functional block diagram of
the deskew circuit. The phase of the sense signal and the
driver signal is presented to a three-input phase comparator
and compared with the reference signal. The phase compara-
tor then controls the voltage controlled delay in the output
drive line to match the delay of the xed reference delay line.
Therefore, the sum of the delay of the driver circuit, PCB
trace delay, rise time delay at the load and the adjustable
delay will always equal the xed maximum delay.
The sense circuit has an internal level detect such that any
skew caused by loading is also accounted for. Since the delay
of the circuit is matched for the entire loop, the phase of all
the drivers are in close alignment at the inputs of the load.
Figure 4. Deskew Circuit Block Diagram.
Load Conditions
The ML6510 has been designed to drive the wide range of
load conditions that are encountered in a high frequency sys-
tem. The eight output clock loads can each vary within a
range of trace length and lumped capacitive load, and the
ML6510 will maintain the low skew characteristics specied
in Electrical Characteristics. The clock skew can be further
minimized by providing some rst-order matching between
any two loads that require particularly well-matched clocks.
The ML6510-80 produces a 5V swing at the load and
requires a single external termination resistor for each out-
put. The FB input pin is connected to the other side of the
termination resistor R1 or R2, with a short connection. Ter-
mination resistor valves should be chosen as follows:
R1 = Z0
R2 = 1.5 x Z0
R3 = 3 x Z0
CLOCK IN
FIXED
MAX
DELAY
PHASE
DETECTOR
SENSE
DRIVE
VOLTAGE
CONTROLLED
DELAY
LOAD
Trace
Impedance
RESISTOR
Values
Z0
R1
R2
R3
40
40
60
120
50
50
75
150
63
63
95
189
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相关代理商/技术参数 |
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