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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 17/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
REV. 1.0.2 12/30/00
9
Figure 3. ML6510 Clock Generation Block Diagram.
and the output frequency is still given by:
fOUT = fVCO/2
R
Note: R implies R1, R0; for -80 version, Not valid: Defaults to
R = 01
The VCO still must remain in the range 80–160 MHz, and
the minimum phase detector input frequency is 625kHz =
(80 MHz/128). Thus the product of (N + 1) and 2R should be
limited to 128:
(N + 1) x 2R
≤ 128
to make sure that the phase detector
inputs remain above the minimum
frequency.
Example: Generating a 2x clock input frequency = 33 MHz
Set R = 01 (output range 40 – 80 MHz), N = 5 (0000101),
M = 2 (000010), M/S = 0
fOUT = fVCO/2
R = 132 MHz/21 = 66 MHz
Example: Generating a 1x clock Input frequency = 66 MHz
Set R = 01 (output range 40–80 MHz), set M = 0 (000000),
N = 0 (0000000), M/S = 0
fOUT = fVCO/2
R = 132 MHz/21 = 66 MHz
For doing frequency multiplication and division, keep M
≥ 2 and N ≥ 2 for the lowest skew between input clock
and output clock. Several congurations for doing
frequency multiplication and division are included in the
8 congurations stored in the on-chip ROM (see PRO-
GRAMMING the ML6510).
PHASE
DETECTOR
÷(M + 1)
[
÷1 TO 64]
LOOP
FILTER
VCO
80-160 MHz
÷2R
MAXIMUM
DELAY
1
0
CM BIT
÷(N + 1)
[
÷1 TO ÷128]
CLKINH
CLKINL
CS BIT
TTL TO ECL
1
0
SYS_CLK
TO DESKEW BUFFERS
ECL INPUT BUFFER
1
0
TEST
RCLKH
RCLKL
R1
R0
INPUT/OUTPUT RANGE
0
80-130 MHz
01
40–80 MHz
10
20–40 MHz
11
10–20 MHz
ff
N
M
MHz
VCO
REF
R
=×
+
()×
+
()
=×
×
=
12
1
33
62
3
132
1
f
MHz
VCO =×
×
=
66
12
1
132
1
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