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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 14/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
6
REV. 1.0.2 12/30/00
Electrical Characteristics (Continued)
Note 1:Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
ML6510 congured with bit CM = 0:
Note: All skew is measured at the device load input pin, NOT at the ML6510 clock output pin. Skew is always positive number,
regardless of which edge is leading and which is trailing.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Programming Timing Characteristics
tRESET
RESET assertion pulse width
50
ns
tA1
AUX mode MCLK high time
2000
ns
tA2
AUX mode MCLK low time
2000
ns
tA3
AUX mode MDOUT data hold time
10
ns
tA4
AUX mode MDOUT data setup time
10
ns
tA5
AUX mode MCLK period
5000
ns
tM1
MAIN mode MCLK high time
900
ns
tM2
MAIN mode MCLK low time
900
ns
tM3
MAIN mode MCLK period
1800
ns
tM4
MAIN mode
MCLK to MDOUT valid
(EEPROM read time)
900
ns
TTL INPUT CLOCK
LOAD [0-7]
1st Order Match
LOAD [0-7] with
no 1st order match
tSKEWF
tSKEWB
tSKEWIO
tSKEWR
PECL INPUT CLOCKS
OR
CLKINH
CLKINL
VICM
AVCC – 0.4V
2.0 V
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