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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 5/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
REV. 1.0.2 12/30/00
13
Table 1. ML6510-80 ROM Codes
Figure 6. AUX Mode Waveform.
Register Denitions
ML6510-80 Shift register chain
CODE
DESCRIPTION
SELECTION BITS
INPUT
FREQ
(MHz)
OUTPUT
FREQ
(MHz)
CONFIGURATION CODE
ROMMSB MCLK MDOUT
CS
CM R1, R0
M
N
TEST
0
PECL Input
Clock, 1x mode
0
40-80
1
01
0
1
PECL Input
Clock, 0.5x mode
0
1
40-80
20-40
1
10
5
2
0
2
PECL Input
Clock, 2x mode
0
1
0
20-40
40-80
1
01
2
5
0
3
PECL Input
Clock, 1x mode
0
1
40-80
1
0
01
0
4
TTL Input Clock,
1x mode
1
0
40-80
0
01
0
5
TTL Input Clock,
0.5x mode
1
0
1
40-80
20-40
0
10
5
2
0
6
TTL Input Clock,
2x mode
1
0
20-40
40-80
0
01
2
5
0
7
TEST mode, TTL
Input clock
1
0-50
0
——
—
1
REGISTER
SIZE
FUNCTION
N
7 bit
This register is used to define the ratio for the desired frequency of the primary clock.
R
2 bit
This register defines the frequency of the primary clocks, CLK [0-7].
CM
1 bit
Set CM = 1 when the PECL input reference clock is from another 6510 reference clock
output. Set CM = 0 if the clock reference is TTL or PECL from an external source and
minimum phase error between input and output is desired.
CS
1 bit
CS = 0 selects TTL input clock, CS = 1 selects PECL input clock.
TEST
1 bit
When set to 1, the PLL is bypassed for low frequency testing.
M
6 bit
This register is used to define the ratio for the desired frequency of the primary clock.
MCLK
(Input to ML6510)
MDOUT
(Input to ML6510)
tA1
tA2
tA5
18
02
01
M5
N0
tA3
tA4
M4
N1
N2
N3
N4
N5
N6
MSB
R0
LSB
R1
MSB
CS
M0
LSB
TEST
M1
M2
M3
M4
M5
MSB
N0
LSB
SERIAL DATA IN
(from EEPROM,
or
Processor,
or internal ROM)
CM
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相关代理商/技术参数 |
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