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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 6/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
14
REV. 1.0.2 12/30/00
Applications
Zero skew clock generation
The most advantageous feature of using PACMan is its abil-
ity to deliver multiple copies of the clock to the load with
very low skew. Because of its unique ability in deskewing,
trace length and load consideration are no longer critical in
board design.
Because of the unique deskewing scheme, neither the trace
length nor the device loads need to be equal. This is true for
loads, <20pF. Higher loads can be driven if they are placed
close to the clock chip, to guarantee signal integrity.
Low skew clock distribution
Clock distribution design is usually not a trivial task,
especially when multiple clock chips are needed. By using
closely grouped PACMans, 16 or more clock lines can be
created with low part-to-part skew. Additional groups of
clocks can be clustered and driven from deskewed clock
lines, to minimize the number of long-distance clock lines.
Board to Board synchronization
Distribution of the synchronous clock could present signi-
cant difculty at high frequency. With the system clock gen-
erated by the ML6510, a zero skew clock delivery to a
backplane is now possible. By using the ML6510 slave chip
or the ML6510 in slave mode at the receiver end, a near zero
delay clock link can be accomplished between the mother
board and the satellite boards.
Because the PACMan has frequency doubling capability, a
lower frequency signal can be used to route across a back plane.
Example conguration
Shown in Figure 7 is an example conguration using two
ML6510-80 chips in tandem to generate eight 66 MHz
clocks and eight 33MHz low-skew clocks from a 66MHz
input reference. This requires only the termination resistors.
Congurations are loaded from the internal ROM. PCB
traces 0 to 15 are each 50
impedance and the load capaci-
tances CL0-CL15 are 0 to 20pF each. No trace length match-
ing is required among separate clock outputs. All traces are
shown with a series termination at the output.
CLOCK
DRIVER
tO–tS2
tO–tS3
tO–tS1
tS1
tS 2
tS3
tS0tS0tS0
ONE
DEVICE
LOAD
TWO
DEVICE
LOAD
THREE
DEVICE
LOAD
CLK2
CLK0
CLK1
ML6510
CLK0
CLK1
CLK2
CLK0
CLK1
ML6510
CLK3
TO REMOTE GROUP
OF CLUSTERED LOADS
ML6510
(SLAVE MODE)
LOAD[0-7]
LOAD[8-15]
33 MHz
tSKEWR (or tSKEWB)
tpp2
tSKEWR (or tSKEWB)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CR | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CT | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6518 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:18 Line Hot-Insertable Active SCSI Terminator |
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