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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 13/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
REV. 1.0.2 12/30/00
5
Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
AC Characteristics rise time, fall time and duty cycle are measured for a generic load;
(see Load Conditions section).
tR
Rise time, LOAD [0-7] output
0.8 2.0V, 80MHz
150
1500
ps
tF
Fall time, LOAD [0-7] output
2.0 0.8V, 80MHz
150
1500
ps
fIN
Input frequency, CLKIN pin
10
80
MHz
fOUT
Output frequency , CLK [0-7]
output
ML6510-80
10
80
MHz
fVCO
PLL VCO operating frequency
80
160
MHz
DC
Output duty cycle
Measured at device load, at
1.5V
40
60
%
tJITTER
Output jitter
Cycle-to-cycle
75
ps
Peak-to-peak
150
ps
tLOCK
PLL and deskew lock time
After programming is
complete
11
ms
Skew Characteristics All skew measurements are made at the load, at 1.5V threshold each output load can vary
independently within the specied range for a generic load (see Load Conditions section).
tSKEWR
Output to output rising
edge skew, all clocks
500
ps
tSKEWF
Output to output
falling edge skew
Output clock frequency
≥
50MHz
1.5
ns
tSKEWIO
CLKIN input to any
LOAD [0-7] output
rising edge skew
N = M = 0
N
≥ 2, M ≥ 2
600
1.25
ps
ns
tRANGE
Round trip delay CLKX to FBX
pin; output CLK period = tCLK
Output frequency < 50MHz
Output frequency
≥ 50MHz
0
10
tCLK/2
ns
tSKEWB
Output-to-output rising edge skew,
between matched loads
Providing first (see LOAD
conditions) order matching
order matching between
outputs
250
ps
Part-To-Part Skew Characteristics Skew measured at the loads, at 1.5V threshold. Reference clock output pins
drive clock input pins of another ML6510.
tPP1
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1, CM = 1
and
N = 0, M = 0;
RCLK outputs to
CLKIN inputs distance less
than 2"
1ns
tPP2
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1,
CM = 1 and
N
≥ 2, M ≥ 2; RCLK outputs
to
CLKIN inputs distance less
than 2"
1ns
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