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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 16/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
8
REV. 1.0.2 12/30/00
Functional Description
Micro Linear’s ML6510 is the rst clock chip to use a
feedback mechanism to adaptively (on a real time basis),
eliminate clock skew in high speed personal computer and
workstation system designs. Figure 1 shows a basic congu-
ration of the ML6510 in a system. The skew problem results
due to the delaying of clock signals in the system, as shown
in Figure 2. Clock skew results from variation in factors like
trace length, PCB trace characteristics, load capacitance,
parasitic capacitance, temperature and supply variations, etc.
Figure 2 shows a representation of the clock skew problem
from a timing perspective. It shows a worst case example
where the clock signal is delayed so much that its rising edge
completely misses the data it is intended to strobe.
Using a clock deskew mechanism, this problem can be
eliminated and the strobe with the appropriate setup and hold
times with respect to the data bus can be generated.
The ML6510 has eight deskew buffers, each with its own
independent the reection and error correction circuit. The
deskew buffer eliminates skew by using the reection from a
remote chip to measure the clock error and then corrects it by
generating the appropriate skew to the clock output to
compensate.
Eight individually deskewed copies of the clock are provided
by the ML6510.
Figure 1. Basic System Configuration Using the ML6510
Figure 2. The Skew Problem
The deskew buffers compensate internally for board-level
skew caused by the PCB trace length variations and device
load variations. This is accomplished by sensing the round
trip delay via a reected signal, and then delaying or advanc-
ing the clock edge so that all 8 output clocks arrive at their
loads in phase. Each of the eight clock lines can have any
length PCB trace (up to 5ns each way or 1/4th of the output
clock period, whichever is smaller) and the device loads can
vary from line to line. The ML6510 will automatically com-
pensate for these variations, keeping the device load clocks
in phase. Although ML6510 will compensate for skew
caused by loading, excessive capacitive loading can cause
rise/fall time degradation at the load. Cascading one
ML6510 to another ML6510 should be done using the PECL
reference clock outputs, to minimize part-to-part skew.
Clock Regeneration
The programmable adaptive clock deskew can function in a
clock regeneration mode to assist in building clock trees or
to expand the number of deskewed clock lines. In this mode,
it has the ability to do clock multiplication or division as
well, while maintaining low skew between input clock and
output clocks. It can thus generate a 2x or 4x or 0.5x fre-
quency multiplication or division from input to output (e.g.
33 MHz input, 66 MHz output or 66 MHz input, 33 MHz
output, etc.). It also can generate a 1x frequency output. The
VCO frequency is dened by:
CPU
MICRO LINEAR
ML6510
CLOCK CHIP
REMOTE
CHIP
CLOCK #0
FEEDBACK #0
CLOCK #1
FEEDBACK #1
CLOCK #7
FEEDBACK #7
DATA
CLOCK
GENERATOR
CLOCK IN
WRITE
SIGNAL
CLOCK AT
REMOTE CHIP
DATA AT
REMOTE CHIP
WRITE
SIGNAL
CLOCK AT
REMOTE CHIP
DATA AT
REMOTE CHIP
DATA
tS
tH
ff
N
M
VCO
REF
R
=×
+
()×
+
()
12
1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ML6510CQ-80 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩) |
| ML6516244 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CR | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6516244CT | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs |
| ML6518 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:18 Line Hot-Insertable Active SCSI Terminator |
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