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参数资料
| 型号： | ML6510CQ80 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 12/17页 |
| 文件大小： | 232K |
| 代理商： | ML6510CQ80 |
ML6510
4
REV. 1.0.2 12/30/00
Electrical Characteristics
The following specications apply over the recommended operating conditions of DVCC = AVCC = 5V ± 5% and ambient
temperature between 0°C and 70°C. Loading conditions are specied individually (Note 1)
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
Supply
DVCCXX
Supply Current for each
pair of clock outputs
fCLKX = 0
50
A
CL= 20pF, ZO = 50
fOUT = 80MHz
40
60
mA
IAVCC1
Static supply current,
AVCC1 pin
100
120
mA
IAVCC2
Static supply current,
AVCC2 pin
35
40
mA
IAVCC3
Static supply current,
AVCC3 pin
12
mA
Low Frequency Inputs and Outputs (ROMMSB, MDOUT, MDIN, MCLK, RESET, LOCK)
VIH
High level input voltage
DVCC – 0.5
V
VIL
Low level input voltage
DGND + 0.5
V
VOH
High level output
voltage,
MCLK and MDIN
IOH = –100 A
DVCC – 0.5
V
VOL
Low level output voltage,
MCLK and MDIN
IOL = +200 A
DGND + 0.5
V
VOH
High level output
voltage, LOCK output
IOH = –100 A
IOH = –10 A
2.4
DVCC – 0.5
V
VOL
Low level output voltage,
LOCK output
IOL = +1 mA
0.4
V
IIN
Static input current
10
A
CIN
Input capacitance
5
pF
High Frequency Inputs and Outputs (CLKINH, CLKINL, FB[0-7], CLK[0-7])
VIH
High level input voltage
CS = 0 (TTL Input Clock)
2.0
V
CS = 1 (PECL Input
Clock)
AVCC – 1.165
AVCC – 0.88
V
VIL
Low level input voltage
CS = 0 (TTL Input Clock)
0.8
V
CS = 1 (PECL Input
Clock)
AVCC – 1.810
AVCC – 1.475
V
VICM
Common mode input
voltage range for PECL
reference clocks
CS = 1 (PECL Input
Clock)
2.0
AVCC – 0.4
V
IIH
High level input current
VIH = 2.4V
100
A
IIL
Low level input current
VIL = 0.4V
–400
A
VOH
High level output voltage IOH = –60mA
2.4
V
VOL
Low level output voltage
IOL = +60mA
0.4
V
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