参数资料
型号: ML6510CQ80
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44
封装: PLASTIC, LCC-44
文件页数: 3/17页
文件大小: 232K
代理商: ML6510CQ80
ML6510
REV. 1.0.2 12/30/00
11
External Input clocks
The external input clock to the ML6510 can be either a
differential Pseudo-ECL clock or a single-ended TTL clock.
This is selected using the CS bit in the serial shift register.
For the single-ended TTL clock tie the CLKINH and CLKINL
pins together. The ML6510 ensures that there is a well-
dened phase difference between the input and output
clocks.
RESET and Lock
When RESET is de-asserted, the internal programming logic
will become active, loading in the conguration bits (see
Programming the ML6510). Once the conguration is
loaded, the PLL will lock onto the reference signal, and then
the deskew blocks will adapt to the load conditions. When all
eight output clocks are stable and deskewed, LOCK will be
asserted. The asserted polarity of lock is high. Thus, LOCK
can be used to indicate that the system is ready, or it can be
used to drive the RESET input of another PACMan in a clock
tree.
RESET may be reasserted at any time to reset the chip
operations. Following a RESET assertion of valid pulse
width (see Programming Electrical Characteristics), the
ML6510 must again be loaded with a conguration, then it
will re-lock and reassert lock when all eight clock outputs
are stable and deskewed.
CHIP
VCC
RESET
LOCK
tRESET
tLOCK
PROGRAM IN THE
CONFIGURATION
PROGRAM IN THE
CONFIGURATION
0
5V
PCB trace impedance
Z0 = 40 to 65
Lumped
CL ≤ 20pF
FBX
CLKX
ML6510-80
FIRST-ORDER
MATCHED LOADS
ML6510-80
GENERIC
LOAD
R1
One way trip delay < tRANGE/2
PCB trace impedance
Z0 = 40 to 65
Lumped
CLX ≤ 20pF
FBX
CLKX
LOAD
R1
Length LX
PCB trace impedance
Z0 = 40 to 65
Lumped
CLY ≤ 20pF
FBY
CLKY
LOAD
R1
One way trip delay < tRANGE/2
Length LY
|CLX – CLY| < 5pF
|LX – LY| < 4"
ZOX = ZOY
相关PDF资料
PDF描述
ML7820A-FBE 20 V FIXED POSITIVE REGULATOR, PSFM3
ML7820FA-FBE 20 V FIXED POSITIVE REGULATOR, PSFM3
ML78L24A-FBL1 24 V FIXED POSITIVE REGULATOR, PBCY3
ML9477 DOT MAT LCD DRVR AND DSPL CTLR, PQFP48
MLF1608K120K 1 ELEMENT, 12 uH, FERRITE-CORE, GENERAL PURPOSE INDUCTOR, SMD
相关代理商/技术参数
参数描述
ML6510CQ-80 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩)
ML6516244 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6516244CR 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6516244CT 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6518 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:18 Line Hot-Insertable Active SCSI Terminator