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参数资料
| 型号： | MPC180LMB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 12/28页 |
| 文件大小： | 356K |
| 代理商： | MPC180LMB |
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MPC180 Hardware Reference Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Overview
1 Overview
The MPC180 is designed to work with Motorola’s PowerQUICC family of processors. The MPC180
interfaces gluelessly to both the PowerQUICC and PowerQUICC II, accelerating the performance of
computationally-intensive security functions, such as key generation and exchange, authentication, and bulk
encryption. Support for 66MHz bus frequencies enables maximum utilization of the MPC8260 local bus as
well as enhanced versions of the MPC8xx system bus.
The MPC180 is optimized to quickly process all the algorithms associated with IPSec, WTLS/WAP,
SSL/TLS, and IKE, including the following:
RSA
RSA signature
Dife-Hellman
Elliptic Curve Cryptography
DES
3DES
SHA-1
MD4
MD5
Arc Four (compatible with RSA’s RC4 algorithm)
The MPC180 works in load/store, memory-mapped systems. An external processor may execute application
code from its ROM and RAM, using RAM and optional nonvolatile memory (such as EEPROM) for storing
data. The MPC180 resides in the processor’s memory map; therefore, an application requiring
cryptographic functions simply writes to and reads from the appropriate memory mapped location of the
MPC180.
As shown in Figure 1 and Figure 2, the MPC180 interfaces to the MPC8xx system bus or to the local bus
of the MPC8260.
Figure 1. MPC850/MPC860 System Example
MPC860
SDRAM
I/O or Network
Interface
System Bus
EEPROM
MPC180
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