参数资料
型号: MPC180LMB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PQFP100
封装: LQFP-100
文件页数: 15/28页
文件大小: 356K
代理商: MPC180LMB
22
MPC180 Hardware Reference Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Timing Analysis
estimates, equations using ‘rules of thumb’ can be used. For this example, we will use the following
equation to estimate the length conversions:
Length = (Calculated Delay +/- Load Delay) / PCB Propagation Speed
(EQ 5)
Load delay = (# of loads) x (capacitance per load (pF)) x (capacitive delay (ps/pF))(EQ 6)
All of the timings used in this analysis are based upon the source driving a 50pF load. If the load that the
source drives is greater than 50pF, the additional delay associated with the extra capacitive load should be
subtracted from the calculated delay. If the load that the source drives is less than 50pF, the additional
margin can be added to the calculated delay. The analysis below assumes that the PCB propagation speed
is 180 psec/inch. An approximate capacitive delay value to use is 35ps/pF.
The input setup margin is now translated into a maximum length restriction. The value is calculated for
when the host processor is the source of the signal and the MPC180 is the receiver. The value physically
represents the maximum distance in inches that should exist between the output pin of the host processor to
the input pin of the MPC180. The results are shown in Table 17.
From the previous section where the timing analysis with clock offset was performed, the results show that
all of the input hold margins are positive. The input hold margin denes the minimum propagation length.
Positive hold margin translates into negative minimum propagation delay. Since no trace can have negative
propagation delay time, the actual hold margin will be the previously calculated hold margin plus the trace
delay of the shortest signal in a given signal group. In this analysis, the minimum PCB length restrictions
are all zero and are shown in Table 18 for completeness.
Table 17. Maximum PCB Length Restriction
Signal
Input Setup Length
with MPC850
Input Setup Length
with MPC860
Input Setup Length
with MPC8260
A[18:29]
30.8 in
32.2 in
22.7 in
ENDIAN
30.8 in
32.2 in
22.7 in
D[0:31]
30.8 in
32.2 in
22.7 in
CS
24.7 in
31.6 in
33.3 in
R/W
30.8 in
32.2 in
22.7 in
BURST
33.8 in
TS
29.4 in
36.3 in
PSDVAL
11.6 in
Table 18. Minimum PCB Length Restriction
Signal
Input Hold Margin
with MPC850
Input Hold Margin
with MPC860
Input Hold Margin
with MPC8260
A[18:29]
0.0 in
ENDIAN
0.0 in
D[0:31]
0.0 in
CS
0.0 in
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