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参数资料
| 型号： | MPC180LMB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 14/28页 |
| 文件大小： | 356K |
| 代理商： | MPC180LMB |
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MOTOROLA
MPC180 Hardware Reference Manual
21
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Timing Analysis
The input setup time margin will now be calculated for when the MPC180 is the source of the signal and
the host processor is the receiver. The results are shown in Table 15.
The input hold time margin will now be calculated for when the host processor is the source of the signal
and the MPC180 is the receiver. The results are shown in Table 16.
7.5 Calculating PCB Trace Lengths
For all previous analysis, units have been measured in nS. Once the nal allowable timing margins are
known, these times must be converted to length rules for PCB routing. Due to the various factors affecting
the actual propagation delays on a PCB it is highly recommended that a SPICE simulator is used to convert
the time delays to length restrictions. However, for those without access to such simulators or for rough
Table 14. MPC180 Input Hold Margin with Clock Offset
Signal
MPC180 Input
Hold Time
MCP850 Hold
Time
MPC860 Hold
Time
MPC8260
Hold Time
Input Hold
Margin with
MPC850
Input Hold
Margin with
MPC860
Input Hold
Margin with
MPC8260
A[18:29]
0.6 nS
5.0 nS
1.0 nS
4.05 nS
0.5 nS
ENDIAN
0.3 nS
5.0 nS
1.0 nS
4.35 nS
0.8 nS
D[0:31]
0.5 nS
5.0 nS
1.0 nS
4.15 nS
0.6 nS
CS
0.4 nS
2.0 nS
1.0 nS
1.25 nS
0.7 nS
R/W
0.5 nS
5.0 nS
1.0 nS
4.15 nS
0.6 nS
BURST
0.3 nS
—
1.0 nS
—
0.8 nS
TS
0.5 nS
5.0 nS
—
4.15 nS
—
PSDVAL
0.3 nS
—
1.0 nS
—
0.8 nS
Table 15. Processor Input Setup Margin with Clock Offset
Signal
MPC180
Access Time
MCP850 Input
Setup Time
MPC860 Input
Setup Time
MPC8260
Input Setup
Time
Input Setup
Margin to
MPC850
Input Setup
Margin to
MPC860
Input Setup
Margin to
MPC8260
D[0:31]
8.9 nS
6.0 nS
5.0 nS
4.75 nS
1.2 nS
TA /
LUPMWAIT
8.5 nS
9.75 nS
6.0 nS
1.4 nS
0.6 nS
DREQx
8.3 nS
—
5.0 nS
—
1.8 nS
Table 16. Processor Input Hold Margin with Clock Offset
Signal
MPC180 Input
Hold Time
MCP850 Hold
Time
MPC860 Hold
Time
MPC8260
Hold Time
Input Hold
Margin to
MPC850
Input Hold
Margin to
MPC860
Input Hold
Margin to
MPC8260
D[0:31]
3.7 nS
1.0 nS
1.25 nS
0.8 nS
TA /
LUPMWAIT
3.5 nS
1.0 nS
1.05 nS
0.6 nS
DREQx
3.4 nS
—
1.0 nS
—
0.5 nS
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