参数资料
型号: MPC180LMB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PQFP100
封装: LQFP-100
文件页数: 13/28页
文件大小: 356K
代理商: MPC180LMB
20
MPC180 Hardware Reference Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Timing Analysis
1. Input hold margin to the MPC180. This can be optimized by having the MPC180 clock arrive
before the host processor clock.
2. Input setup margin to the host processor. This can be optimized by having the MPC180 clock
arrive before the host processor clock.
Since the two areas that need optimization require the clock offset to be adjusted in the same direction, the
PCB designer can intentionally offset the clock that drives the host processor in reference to the clock that
drives the MPC180 to maximize the timing margins. By adjusting the offset such that the clock to the
MPC180 arrives in time before the clock to the host processor, the input setup margin to the MPC180 can
be exchanged for input hold margin to the MPC180 and input hold margin to the host processor can be
exchanged for input setup margin to the host processor.
In choosing the appropriate clock offset, the PCB designers should make appropriate trade-offs in order to
balance the margin. In this analysis, 0.55 nS was chosen for the MPC850 and MPC860 in order to balance
the Data hold to the host processor with the CS hold to the MPC180. An offset of 1.0 nS was chosen for the
MPC8260 interface to balance the Data input hold to the MPC180 with the TA output hold to the MPC8260.
The following clock offsets will now be taken into consideration and the timing analysis will be repeated:
tclock_offset = 055 nS for the MPC850 and MPC860 (The clock that drives the MPC180 should
arrive 0.55 nS in absolute time before the clock that drives the MPC850 and MPC860)
tclock_offset = 1.0 nS for the MPC8260 (The clock that drives the MPC180 should arrive 1.0 nS in
absolute time before the clock that drives the MPC8260)
The input setup time margin is calculated for when the host processor is the source of the signal and the
MPC180 is the receiver. The results are shown in Table 13.
The input hold time margin will now be calculated for when the host processor is the source of the signal
and the MPC180 is the receiver. The results are shown in Table 14.
Table 13. MPC180 Input Setup Margin with Clock Offset
Signal
MPC180 Input
Setup Time
MCP850
Access Time
MPC860
Access Time
MPC8260
Access Time
Input Setup
Margin with
MPC850
Input Setup
Margin with
MPC860
Input Setup
Margin with
MPC8260
A[18:29]
1.0 nS
12.0 nS
11.75 nS
8.0 nS
5.55 nS
5.8 nS
4.1 nS
ENDIAN
1.0 nS
12.0 nS
11.75 nS
8.0 nS
5.55 nS
5.8 nS
4.1 nS
D[0:31]
1.0 nS
12.0 nS
11.75 nS
8.0 nS
5.55 nS
5.8 nS
4.1 nS
CS
1.1 nS
13.0 nS
11.75 nS
6.0 nS
4.45 nS
5.7 nS
6.0 nS
R/W
1.0 nS
12.0 nS
11.75 nS
6.0 nS
5.55 nS
5.8 nS
6.1 nS
BURST
1.0 nS
6.0 nS
6.1 nS
TS
1.0 nS
12.25 nS
11.0 nS
5.3 nS
6.55 nS
PSDVAL
1.0 nS
10.0 nS
2.1 nS
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