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参数资料
| 型号： | MPC180LMB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 24/28页 |
| 文件大小： | 356K |
| 代理商： | MPC180LMB |
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MOTOROLA
MPC180 Hardware Reference Manual
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Descriptions
4 Signal Descriptions
Table 1. Pin Descriptions
Signal name
Pin
locations
Signal
type
Description
Signal pins
A[18:29]
62, 64, 66,
67, 68, 70,
72–75, 77,
78
I
Address—address bus from the processor core. These bits are decoded in the
MPC180 to produce the individual module select lines to the execution units. Note
that the processor address bus might be 32 bits wide, while the MPC180 address
bus is only 12 bits wide.
msb = bit 0
lsb = bit 31
D[0:31]
38, 32, 28,
18, 12, 6,
99, 92, 37,
31, 24, 17,
11, 4, 98,
90, 36, 30,
22, 16, 9, 2,
96, 89, 34,
29, 20, 14,
7, 1, 94, 87
I/O
Data—bidirectional data bus. This bus is connected directly to the processor core.
msb = bit 0
lsb = bit 31
CS
56
I
Chip Select. Active low signal that indicates when a data transfer is intended for
the MPC180.
R/W
54
I
Read/Write. Read/write line
1 read cycle
0 write cycle
BURST
55
I
Burst Transaction. Active low signal used in the 8260 interface that indicates when
the current read/write is a burst transfer.
TS
53
I
Transfer Start. Transfer start pin for control port. This signal is asserted by the
850/860 to indicate the start of a bus cycle that transfers data to or from the
MPC180. This is used by the MPC180 along with CS, R/W, and A to begin a
transfer.
PSDVAL
82
I
Data valid. This active low signal is ignored when CONFIG=0 (MPC860 Mode),
but is active in MPC8260 Mode. The assertion of PSDVAL indicates that a data
beat is valid on the data bus.
TA /
LUPMWAIT
61
O
Transfer Acknowledge. This active low signal is used in 860 mode and is asserted
by the MPC180 when a successful read or write has occurred.
Local UPM wait. This active high signal is used in 8260 mode and is asserted to
indicate the number of wait states for a transaction.
Miscellaneous pins
RESET
52
I
Reset. Asynchronous reset signal for initializing the chip to a known state. It is
highly recommended that this signal be connected to a dual hardware/software
reset function. Thus, the system designer can reset the MPC180 chip with optimal
exibility.
CONFIG
57
I
Conguration. Input that indicates whether the interface is to an MPC860 or
MPC8260
1 8260 interface
0 860 interface
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