参数资料
型号: MPC180LMB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PQFP100
封装: LQFP-100
文件页数: 25/28页
文件大小: 356K
代理商: MPC180LMB
6
MPC180 Hardware Reference Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Descriptions
ENDIAN
40
I
Endian. Active high for big endian mode. Low for little endian mode
1 big endian
0 little endian
IRQ
85
O
Interrupt Request. Interrupt line that signies that one or more execution units
modules has asserted its IRQ hardware interrupt.
NC
26, 27, 49,
50, 51, 76,
100
No connection to the pin
DMA Hardware Handshake pins
DREQ1
83
O
DMA Request 1. Active high signal which indicates that either the input or output
buffer is requesting data transfer by the host or DMA controller. DREQ1 and
DREQ2 are each programmable to refer to the MPC180 chip input buffer or output
buffer. This signal is designed to interoperate with a PowerQUICC IDMA channel.
DREQ2
84
O
DMA request 2. Active high signal which indicates that either the input or output
buffer is requesting data transfer by the host or DMA controller. DREQ1 and
DREQ2 are each programmable to refer to the MPC180 Chip input buffer or output
buffer. This signal is designed to interoperate with a PowerQUICC IDMA channel.
Clock
CLK
59
I
Master clock input
Test
TCK
47
I
JTAG test clock
If JTAG is NOT used, this pin should be tied to OVSS
TDI
48
I
JTAG test data input
If JTAG is NOT used, this pin should be tied to OVDD
TDO
44
I
JTAG test data output
If JTAG is NOT used, this pin should be NC
TMS
46
I
JTAG test mode select
If JTAG is NOT used, this pin should be tied to OVDD
TRST
45
I
JTAG test reset
If JTAG is NOT used, this pin should be tied to OVSS
Power and Ground
IVDD
10, 21, 41,
60, 71, 93
I
+1.8 Volts (power pins for core logic)
OVDD
5, 15, 25,
35, 43, 65,
81, 88, 97
I
+3.3 Volts (Power pins for I/O pads)
OVSS
3, 13, 23,
33, 42, 63,
79, 80, 86,
95
I
0 Volts (Ground)
IVSS
8, 19, 39,
58, 69, 91
I
0 Volts (Ground)
Table 1. Pin Descriptions (continued)
Signal name
Pin
locations
Signal
type
Description
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