15-6
MPC561/MPC563 Reference Manual
MOTOROLA
QSMCM Global Registers
The QSMCM assignable data space segment contains the control and status registers for
the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM can be
accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries. Word accesses
require two consecutive IMB3 bus cycles.
15.4 QSMCM Global Registers
The QSMCM global registers contain system parameters used by the QSPI and dual SCI
submodules for interfacing to the CPU and the intermodule bus. The global registers are
15.4.1
Low-Power Stop Operation
When the STOP bit in QSMCMMCR is set, the IMB3 clock input to the QSMCM is
disabled and the module enters a low-power operating state. QSMCMMCR is the only
register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable
in low-power stop mode. However, writes to RAM or any register are guaranteed valid
while STOP is asserted. STOP can be written by the CPU and is cleared by reset.
System software must bring each submodule to an orderly stop before setting STOP to
avoid data corruption. The SCI receiver and transmitter should be disabled after transfers
in progress are complete. The QSPI can be halted by setting the HALT bit in SPCR3 and
then setting STOP after the HALTA flag is set in SPSR.
15.4.2
Freeze Operation
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3
FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debug
mode. Setting FRZ1 causes the QSPI to halt on the first transfer boundary following
FREEZE assertion. FREEZE causes the SCI1 transmit queue to halt on the first transfer
boundary following FREEZE assertion.
Table 15-2. QSMCM Global Registers
Access 1
1 S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
Address
MSB
2
0
2 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
LSB
15
S
0x30 5000
QSMCM Module Configuration Register (QSMCMMCR)
T
0x30 5002
QSMCM Test Register (QTEST)
S
0x30 5004
Dual SCI Interrupt Level (QDSCI_IL)
Reserved
S
0x30 5006
Reserved
Queued SPI Interrupt Level (QSPI_IL)