MOTOROLA
Chapter 16. CAN 2.0B Controller Module
16-21
Interrupts
Unlike other modules, the TouCAN does not come out of reset in low-power stop
mode. The basic TouCAN initialization procedure should be executed before
If the TouCAN is in low-power stop mode with the self wake mechanism engaged
and is operating with a single system clock per time quantum, there can be extreme
cases in which the TouCAN would wake-up on a recessive to dominant edge which
may not conform to the CAN protocol. TouCAN synchronization is shifted one time
quantum from the wake-up event. This shift lasts until the next
recessive-to-dominant edge, which resynchronizes the TouCAN to be in
conformance with the CAN protocol. The same holds true when the TouCAN is in
auto power save mode and awakens on a recessive to dominant edge.
16.5.3
Auto Power Save Mode
Auto power save mode enables normal operation with optimized power savings. Once the
auto power save (APS) bit in CANMCR is set, the TouCAN looks for a set of conditions in
which there is no need for the clocks to be running. If these conditions are met, the TouCAN
stops its clocks, thus saving power. The following conditions activate auto power save
mode:
No Rx/Tx frame in progress
No transfer of Rx/Tx frames to and from a serial message buffer, and no Tx frame
awaiting transmission in any message buffer
No CPU access to the TouCAN module
The TouCAN is not in debug mode, low-power stop mode, or the bus off state
While its clocks are stopped, if the TouCAN senses that any one of the aforementioned
conditions is no longer true, it restarts its clocks. The TouCAN then continues to monitor
these conditions and stops or restarts its clocks accordingly.
16.6 Interrupts
The TouCAN can generate one interrupt level to be passed to the CPU. This level is
programmed into the priority level bits in the interrupt configuration register (CANICR).
This value determines which interrupt signal is driven onto the bus when an interrupt is
requested.
Each one of the 16 message buffers can be an interrupt source, if its corresponding IMASK
bit is set. There is no distinction between transmit and receive interrupts for a particular
buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG bit is set when
the corresponding buffer completes a successful transmission/reception. An IFLAG bit is