19-12
MPC561/MPC563 Reference Manual
MOTOROLA
Programming Model
19.4.2
Development Support Control Register (DSCR)
3:4
TCR2P
Timer Count Register 2 prescaler control. TCR2 is clocked from the output of a prescaler. The
prescaler divides this input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
5
EMU
Emulation control. In emulation mode, the TPU3 executes microinstructions from DPTRAM
exclusively. Access to the DPTRAM via the IMB3 is blocked, and the DPTRAM is dedicated for
use by the TPU3. After reset, this bit can be written only once.
0 TPU3 and DPTRAM operate normally
1 TPU3 and DPTRAM operate in emulation mode 1
6
T2CG
TCR2 clock/gate control
0 TCR2 pin used as clock source for TCR2
1 TCR2 pin used as gate of DIV8 clock for TCR2
7
STF
Stop flag.
0 TPU3 is operating normally
1 TPU3 is stopped (STOP bit has been set)
8
SUPV
Supervisor data space
0 Assignable registers are accessible from user or supervisor privilege level
1 Assignable registers are accessible from supervisor privilege level only
9
PSCK
Standard prescaler clock. Note that this bit has no effect if the extended prescaler is selected
(EPSCKE = 1).
0fSYS ÷ 32 is input to TCR1 prescaler, if standard prescaler is selected
1fSYS ÷ 4 is input to TCR1 prescaler, if standard prescaler is selected
10
TPU3
TPU3 enable. The TPU3 enable bit provides compatibility with the TPU. If running TPU code on
the TPU3, the microcode size should not be greater than 2 Kbytes and the TPU3 enable bit
should be cleared to zero. The TPU3 enable bit is write-once after reset. The reset value is one,
meaning that the TPU3 will operate in TPU3 mode.
0 TPU mode; zero is the TPU reset value
1 TPU3 mode; one is the TPU3 reset value
NOTE: The programmer should not change this value unless necessary when developing custom
TPU microcode.
11
T2CSL
TCR2 counter clock edge. This bit and the T2CG control bit determine the clock source for TCR2.
12:15
—
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TPU3
implementations that use hardware interrupt arbitration.
1 If all TPUs connected to a DPTRAM are stopped, the DPTRAM is accessible.
Table 19-7. TPUMCR Bit Description (continued)
Bits
Name
Description