MOTOROLA
Chapter 13. QADC64E Legacy Mode Operation
13-55
Digital Subsystem
Example 1 in
Table 13-21 shows that when the PSH = 19, the QCLK remains high for 20
cycles if the IMB3 clock and with PSL = 7 the QCLK remains low for 8 IMB3 clock cycles.
Example 2 shows that when PSH = 11, QCLK is high for 12 IMB3 clock cycles and with
PSL = 7, QCLK is low for 8 IMB3 clock cycles. Finally, example 3 shows that with
PSH = 7 and PSL = 7, QCLK alternates between high and low every 8 IMB3 cycles.
13.5.6
Periodic / Interval Timer
The on-chip periodic/interval timer can be used to generate trigger events at a
programmable interval, initiating execution of queue 1 and/or queue 2. The
periodic/interval timer stays reset under the following conditions:
Both queue 1 and queue 2 are programmed to any mode which does not use the
periodic/interval timer
IMB3 system reset or the master reset is asserted
Stop mode is selected
Freeze mode is selected
NOTE
Interval
timer
single-scan
mode
does
not
use
the
periodic/interval timer until the single-scan enable bit is set.
The following two conditions will cause a pulsed reset of the periodic/interval timer during
use:
A queue 1 operating mode change to a mode which uses the periodic/interval timer,
even if queue 2 is already using the timer
A queue 2 operating mode change to a mode which uses the periodic/interval timer,
provided queue 1 is not in a mode which uses the periodic/interval timer
Roll over of the timer
During the low power stop mode, the periodic timer is held in reset. Since low power stop
mode causes QACR1 and QACR2 to be reset to zero, a valid periodic or interval timer
mode must be written after stop mode is exited to release the timer from reset.
When the IMB3 internal FREEZE line is asserted and a periodic or interval timer mode is
selected, the timer counter is reset after the conversion in progress completes. When the
periodic or interval timer mode has been enabled (the timer is counting), but a trigger event
has not been issued, the freeze mode takes effect immediately, and the timer is held in reset.
When the internal FREEZE line is negated, the timer counter starts counting from the
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