25-2
MPC561/MPC563 Reference Manual
MOTOROLA
IEEE 1149.1 Test Access Port
IEEE1149.1 Compatibility Exceptions:
The MPC561/MPC563 enters JTAG mode by going through a standard device reset
sequence with the JCOMP signal asserted high during PORESET negation. Once
JTAG has been entered, the MPC561/MPC563 remains in JTAG mode until another
reset sequence is applied to exit JTAG mode, or the device is powered down.
The JTAG output port, TDO, is configured with a weak pull-up until reset negates
or the driver is disabled.
The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data
registers. A boundary scan register links all device signal pins into a single shift register.
The test logic implemented utilizes static logic design. The MPC561/MPC563
implementation provides the capability to:
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the MPC561/MPC563 for a given circuit-board test by effectively reducing
the boundary scan register to a single cell.
3. Sample the MPC561/MPC563 system pins during operation and transparently shift
out the result in the boundary scan register.
4. Disable the output drive to pins during circuit-board testing.
NOTE
Certain precautions must be observed to ensure that the IEEE
1149-like test logic does not interfere with nontest operation.
JCOMP must be low prior to PORESET assertion after low
power mode exits, otherwise an unknown state will occur.
25.1.1
Overview
An overview of the MPC561/MPC563 scan chain implementation is shown in
Figure 25-2.The MPC561/MPC563 implementation includes a TAP controller, a 4-bit instruction
register, and two test registers (a one-bit bypass register and a 427-bit (MPC563) or 423-bit
(MPC561) boundary scan register). This implementation includes a dedicated TAP
consisting of the following signals:
TCK — a test clock input to synchronize the test logic. (with an internal pull-down
resistor)
TMS — a test mode select input (with an internal pullup resistor) that is sampled on
the rising edge of TCK to sequence the TAP controller’s state machine.
TDI — a test data input (with an internal pullup resistor) that is sampled on the rising
edge of TCK.