MOTOROLA
Chapter 3. Central Processing Unit
3-53
Operating Environment Architecture (OEA)
The operand of a load or store multiple instruction is not word-aligned.
The operand of lwarx or stwcx. is not word-aligned.
Alignment exceptions use the SRR0 and SRR1 to save the machine state and the DSISR to
determine the source of the exception.
The register settings for alignment exceptions are shown in
Table 3-27.
Table 3-27. Register Settings for Alignment Exception
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0) 1
1 If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Set to the effective address of the instruction that caused the
exception.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Other
Cleared to 0
Data/Storage Interrupt Status
Register (DSISR)
[0:11]
Cleared to 0
[12:13]
Cleared to 0
14
Cleared to 0
[15:16]
For instructions that use register indirect with index addressing,
set to bits [29:30] of the instruction.
For instructions that use register indirect with immediate index
addressing, cleared.
17
For instructions that use register indirect with index addressing,
set to bit 25 of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bit 5 of the instruction.
[18:21]
For instructions that use register indirect with index addressing,
set to bits [21:24] of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bits [1:4] of the instruction.
[22:26]
Set to bits [6:10] (source or destination) of the instruction.
[27:31]
Set to bits [11:15] of the instruction (rA). Set to either bits [11:15]
of the instruction or to any register number not in the range of
registers loaded by a valid form instruction, for lmw, lswi, and
lswx instructions. Otherwise undefined.