MOTOROLA
Chapter 10. Memory Controller
10-37
Programming Model
10.9.5
Dual-Mapping Base Register (DMBR)
,
28:30
BSCY
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus
using SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is (1 + BSCY) x Clocks.
If an external TA response has been selected for this memory bank (by setting the SETA bit) then
BSCY[0:3] are not used.
000 0-clock-cycle (1 clock per data beat)
001 1-clock-cycle wait states (2 clocks per data beat)
010 2-clock-cycle wait states (3 clocks per data beat)
011 3-clock-cycle wait states (4 clocks per data beat)
1xx Reserved
Following a system reset, the BSCY bits are set to 0b011 in OR0.
31
TRLX
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory
devices during a memory access to this memory region. Relaxed timing multiplies by two the
number of wait states determined by the SCY and BSCY fields. Refer to
Section 10.3.5,0 Normal timing is generated by the GPCM.
1 Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR0.
MSB
0123456789
10
11
12
13
14
15
Field
—
BA
—
AT
—
HRESET
0
Undefined
000
001
000
Addr
0x2F C140
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
Field
—
DMCS
DME
HRESET
0000_0000_0000_0
ID201
1 The reset value is a reset configuration word value extracted from the indicated internal data bus lines. Refer to
Figure 10-25. Dual-Mapping Base Register (DMBR)
Table 10-12. DMBR Bit Descriptions
Bits
Name
Description
0—
Reserved
1:6
BA
Base address. BA field corresponds to address bits [11:16]. The base address field is
compared (along with the address type field) to the address of the address bus to determine
whether an address should be dual-mapped by one of the memory banks controlled by the
memory controller. These bits are used in conjunction with the AM[11:16] bits in the DMOR.
Table 10-11. OR0–OR3 Bit Descriptions (continued)
Bits
Name
Description