MOTOROLA
Chapter 2. Signal Descriptions
2-23
Pad Module Configuration Register (PDMCR2)
2.4
Pad Module Configuration Register (PDMCR2)
The PDMCR2 controls alternate functionality of signals shared between different modules,
as well as the pre-discharge circuitry to allow 5V friendliness on the data bus.
6
PRDS
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by the PRDS bit include the following:
all SGPIO signals
all TPU3 signals
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
7
SPRDS
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by the SPRDS bit include the following: BDIP, TA, TS, TEA, RD/WR, BR, BG, BB,
TSIZ, BI/STS, BURST, TDI, TMS, JCOMP, TCK.
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
Refer to
Table 2-12 for more information on SPRDS.
8
T2CLK_PU Controls the pull-up on the TPU T2CLK signals.
0 Pull-ups are enabled if the T2CLK signals are defined as inputs
1 Pull-ups are disabled on the T2CLK signals
9:14
PULL_DIS
Disables weak pull up-or-down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by these bits include the following:
PULL_DIS0 (bit 9): all MIOS14 input signals
PULL_DIS1 (bit 10): all QSMCM input signals
PULL_DIS2 (bit 11): all QADC64E input signals, except ETRIG1 and ETRIG2
PULL_DIS3 (bit 12): all TouCAN input signals
PULL_DIS4 (bit 13): Reserved
PULL_DIS5 (bit 14): ETRIG1 and ETRIG2 1
0 Enable weak pull-up/pull-down devices on pads controlled by this signal.
1 Disable weak pull-up/pull-down devices on pads controlled by this signal.
15-31
—
Reserved
1 This bit was RESERVED on the K27S mask set of MPC561.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field PREDIS_ EN
—
TCNC
MPI7 MPI8 MPI9
—
PPMPAD
—
HRESET
0000_0000_0000_0000
Addr
0x2F C038
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB
31
Field
PPMV
—
MDO6 MPI6
—
PC
SV
PCS
4EN
PCS
5EN
PCS
6EN
PCS
7EN
—
HRESET
0000_0000_0000_0000
Figure 2-3. Pads Module Configuration Register 2 (PDMCR2)
Table 2-5. PDMCR Field Descriptions (continued)
Bits
Name
Description