MOTOROLA
Appendix F. Electrical Characteristics
F-19
Issues Regarding Power Sequence
F.9
Issues Regarding Power Sequence
F.9.1
Application of PORESET or HRESET
When VDDH is rising and VDDL is at 0.0 V, as VDDH reaches 1.6 V, all 5 V drivers are
tristated. Before VDDH reaches 1.6V, all 5 V outputs are unknown. If VDDL is rising and
VDDH is at least 3.1V greater than VDDL, then the 5 V drivers can come out of tristate when
VDDL reaches 1.1V, and the 2.6 V drivers can start driving when VDDL reaches 0.5 V. For
these reasons, the PORESET or HRESET signal must be asserted during power-up before
VDDL is above 0.5 V.
If the PORESET or HRESET signal is not asserted before this condition, there is a
possibility of disturbing the programmed state of the flash. In addition, the state of the pads
are indeterminant until PORESET or HRESET propagates through the device to initialize
all circuitry.
F.9.2
Keep-Alive RAM
PORESET or HRESET must be asserted during power-down prior to any supply dropping
out of specified operating conditions.
An additional constraint is placed on PORESET assertion since it is an asynchronous input.
To assure that the assertion of PORESET does not potentially cause stores to keep-alive
RAM to be corrupted (store single or store multiple) or non-coherent (store multiple), either
of the following solutions is recommended:
Assert HRESET at least 0.5
s prior to when PORESET is asserted.
Assert IRQ0 (non-maskable interrupt) at least 0.5 s prior to when PORESET is
asserted. The service routine for IRQ0 should not perform any writes to keep-alive
RAM.
The amount of delay that should be added to PORESET assertion is dependent upon the
frequency of operation and the maximum number of store multiples executed that are
required to be coherent. If store multiples of more than 28 registers are needed and if the
frequency of operation is lower that 56 MHz, the delay added to PORESET assertion will
need to be greater than 0.5 s. In addition, if KAPWR features are being used, PORESET
should not be driven low while the VDDH and VDDL supplies are off.
F.10 AC Timing
Figure F-9 displays generic examples of MPC561/MPC563 timing. Specific timing