20-8
MPC561/MPC563 Reference Manual
MOTOROLA
DPTRAM Operation
Reset will also reconfigure some of the fields and bits in the DPTRAM control registers to
their default reset state. See the description of the control registers to determine the effect
of reset on these registers.
20.4.4
Stop Operation
Setting DPTMCR[STOP] causes the module to enter its lowest power-consuming state.
The DPTMCR can still be written to allow the STOP control bit to be cleared.
In stop mode, the DPTRAM array cannot be read or written. All data in the array is retained
The BIU continues operating to allow the CPU to access the STOP bit in the DPTMCR.
The system clock remains stopped until the STOP bit is cleared or the DPTRAM module is
reset.
The STOP bit is initialized to logical zero during reset. Only the STOP bit in the DPTMCR
can be accessed while the STOP bit is asserted. Accesses to other DPTRAM registers may
result in unpredictable behavior.
The DPTRAM will not enter stop mode if one of the TPUs is in emulation mode using
DPTRAM (i.e., TPUMCR[EMU] = 1)
20.4.5
Freeze Operation
The FREEZE line on the IMB3 has no effect on the DPTRAM module. When the freeze
line is set, the DPTRAM module will operate in its current mode of operation. If the
DPTRAM module is not disabled, (RAMDS = 0), it may be accessed via the IMB3. If the
DPTRAM array is being used by the TPU3 in emulation mode, the DPTRAM will still be
able to be accessed by the TPU3 microengine.
20.4.6
TPU3 Emulation Mode Operation
To emulate TPU3 time functions, store in the RAM array the microinstructions required for
all time functions. Storing microinstructions must be done with the DPTRAM in its normal
operating mode and accessible from the IMB3. After the time functions are stored in the
array, place one or both of the TPU3 units in emulation mode. The RAM array is then
controlled by the TPU3 units and disconnected from the IMB3.
To use the DPTRAM for microcode accesses, set the EMU bit in the corresponding TPU3
module configuration register. Through the auxiliary buses, the TPU3 units can access
word instructions simultaneously at a rate of up to 56 MHz.
When the DPTRAM array is being used by one or two of the TPU3 units, all accesses via
the IMB3 are disabled. The control registers have no effect on the RAM array.