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| 型号： | MPC8313E-RDB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/99页 |
| 文件大小： | 0K |
| 描述： | BOARD PROCESSOR |
| 产品培训模块： | MPC8313E PowerQUICC Processor MPC8314/15 Product Overview |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MCU |
| 适用于相关产品： | MPC8313E |
| 所含物品： | 参考设计板、软件和说明文档 |
| 相关产品： | MPC8313VRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313EZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313EVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ECZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ECVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313CZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313CVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ZQAFF-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ZQADD-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313VRAFF-ND - IC MPU POWERQUICC II PRO 516PBGA 更多... |
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MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
14
Freescale Semiconductor
5.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications.
This table provides the PLL lock times.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that
DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock and power applied to
SYS_CLK_IN when the device is in PCI host mode
32
—
tSYS_CLK_IN
2
Required assertion time of PORESET with stable clock and power applied to
PCI_SYNC_IN when the device is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET assertion (output)
512
—
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]
and CFG_CLK_IN_DIV) with respect to negation of PORESET when the
device is in PCI host mode
4—
tSYS_CLK_IN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]
and CFG_CLKIN_DIV) with respect to negation of PORESET when the
device is in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of
HRESET
0—
ns
—
Time for the device to turn off POR configuration signal drivers with respect
to the assertion of HRESET
—4
ns
3
Time for the device to turn on POR configuration signal drivers with respect to
the negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the
primary clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.
2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Note
PLL lock times
—
100
s—
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8313E-RDBB | 功能描述:开发板和工具包 - 其他处理器 CPU BOARD VER 2.1 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8313E-RDBB | 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| MPC8313E-RDBC | 功能描述:开发板和工具包 - 其他处理器 8313E CPU board Ver 2.2 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8313EVRADD | 制造商:Freescale Semiconductor 功能描述:MPC83XX RISC 32-BIT 90NM 333MHZ 1V/1.8V/2.5V/3.3V 516-PIN TE - Trays |
| MPC8313EVRADDB | 功能描述:微处理器 - MPU PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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