- 您现在的位置：买卖IC网 > PDF目录17049 > MPC8313E-RDB (Freescale Semiconductor)BOARD PROCESSOR PDF资料下载
参数资料
| 型号： | MPC8313E-RDB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 98/99页 |
| 文件大小： | 0K |
| 描述： | BOARD PROCESSOR |
| 产品培训模块： | MPC8313E PowerQUICC Processor MPC8314/15 Product Overview |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MCU |
| 适用于相关产品： | MPC8313E |
| 所含物品： | 参考设计板、软件和说明文档 |
| 相关产品： | MPC8313VRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313EZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313EVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ECZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ECVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313CZQAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313CVRAFFB-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ZQAFF-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313ZQADD-ND - IC MPU POWERQUICC II PRO 516PBGA MPC8313VRAFF-ND - IC MPU POWERQUICC II PRO 516PBGA 更多... |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页当前第98页第99页
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
98
Freescale Semiconductor
1
3/2008
In Table 63, added LBC_PM_REF_10 & LSRCID3 as muxed with USBDR_PCTL1
In Table 63, added LSRCID2 as muxed with USBDR_PCTL0
In Table 63, added LSRCID1 as muxed with USBDR_PWRFAULT
In Table 63, added LSRCID0 as muxed with USBDR_DRIVE_VBUS
In Table 63, moved T1, U2,& V2 from VDD to XCOREVDD.
In Table 63, moved P2, R2, & T3 from VSS to XCOREVSS.
In Table 63, moved P5, & U4 from VDD to XPADVDD.
In Table 63, moved P3, & V4 from VSS to XPADVSS.
In Table 63, removed “Double with pad” for AVDD1 and AVDD2 and moved AVDD1 and AVDD2 to Power
and Ground Supplies section
In Table 63, added impedance control requirements for SD_IMP_CAL_TX (100 ohms to GND) and
SD_IMP_CAL_RX (200 ohms to GND).
In Table 63, updated muxing in pinout to show new options for selecting IEEE 1588 functionality. Added
footnote 8
In Table 63, updated muxing in pinout to show new LBC ECC boot enable control muxed with
eTSEC1_MDC
Added pin type information for power supplies.
Removed N1 and N3 from Vss section of Table 63. Added Therm0 and Therm1 (N1 and N3,
respectively). Added note 7 to state: “Internal thermally sensitive resistor, resistor value varies linearly
with temperature. Useful for determining the junction temperature.”
In Table 65 corrected maximum frequency of Local Bus Frequency from “33–66” to 66 MHz
In Table 65 corrected maximum frequency of PCI from “24–66” to 66 MHz
Added “which is determined by RCWLR[COREPLL],” to the note in Section 20.2, “Core PLL
Configuration” about the VCO divider.
Added “(VCOD)” next to VCO divider column in Table 68. Added footnote stating that core_clk
frequency must not exceed its maximum, so 2.5:1 and 3:1 core_clk:csb_clk ratios are invalid for certain
csb_clk values.
In Table 69, notes were confusing. Added note 3 for VCO column, note 4 for CSB (csb_clk) column,
note 5 for USB ref column, and note 6 to replace “Note 1”. Clarified note 4 to explain erratum eTSEC40.
In Table 69, updated note 6 to specify USB reference clock frequencies limited to 24 and 48 for rev. 2
silicon.
Replaced Table 71 “Thermal Resistance for TEPBGAII with Heat Sink in Open Flow”.
Removed last row of Table 19.
Removed 200 MHz rows from Table 21 and Table 5.
Changed VIH minimum spec from 2.0 to 2.1 for clock, PIC, JTAG, SPI, and reset pins in Table 9,
Table 47, Table 54, Table 59, and Table 61.
Added Figure 4 showing the DDR input timing diagram.
In Table 19, removed “MDM” from the “MDQS-MDQ/MECC/MDM” text under the Parameter
column for the tCISKEW parameter. MDM is an output signal and should be removed from
the input AC timing spec table (tCISKEW).
Added “and power” to rows 2 and 3 in Table 10
Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power
Sequencing,” and Figure 3.
In Figure 35, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK”
In Table 42, clarified that AC specs are for ULPI only.
0
6/2007
Initial release.
Table 73. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
相关PDF资料 |
PDF描述 |
|---|---|
| STD01W-J | WIRE & CABLE MARKERS |
| STD09W-C | WIRE & CABLE MARKERS |
| STD09W-T | WIRE & CABLE MARKERS |
| MLK1005S18NJ | INDUCTOR MULTILAYER 18NH 0402 |
| STD02W-R | WIRE & CABLE MARKERS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8313E-RDBB | 功能描述:开发板和工具包 - 其他处理器 CPU BOARD VER 2.1 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8313E-RDBB | 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| MPC8313E-RDBC | 功能描述:开发板和工具包 - 其他处理器 8313E CPU board Ver 2.2 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8313EVRADD | 制造商:Freescale Semiconductor 功能描述:MPC83XX RISC 32-BIT 90NM 333MHZ 1V/1.8V/2.5V/3.3V 516-PIN TE - Trays |
| MPC8313EVRADDB | 功能描述:微处理器 - MPU PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。